[Beignet] [PATCH 1/2] support 64bit-integer reading(writing)
Zhigang Gong
zhigang.gong at gmail.com
Tue Aug 6 00:12:32 PDT 2013
LGTM, pushed, thanks.
On Tue, Aug 06, 2013 at 02:24:34PM +0800, Homer Hsing wrote:
>
> Signed-off-by: Homer Hsing <homer.xing at intel.com>
> ---
> backend/src/backend/gen_context.cpp | 8 ++---
> backend/src/backend/gen_context.hpp | 4 +--
> backend/src/backend/gen_encoder.cpp | 4 +--
> backend/src/backend/gen_encoder.hpp | 8 ++---
> .../src/backend/gen_insn_gen7_schedule_info.hxx | 4 +--
> backend/src/backend/gen_insn_selection.cpp | 34 ++++++++++++----------
> backend/src/backend/gen_insn_selection.hxx | 4 +--
> backend/src/ir/instruction.cpp | 1 +
> 8 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
> index 252002c..3d8ed1c 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -357,7 +357,7 @@ namespace gbe
> // For SIMD8, we allocate 2*elemNum temporary registers from dst(0), and
> // then follow the real destination registers.
> // For SIMD16, we allocate elemNum temporary registers from dst(0).
> - void GenContext::emitReadFloat64Instruction(const SelectionInstruction &insn) {
> + void GenContext::emitRead64Instruction(const SelectionInstruction &insn) {
> const uint32_t elemNum = insn.extra.elem;
> const uint32_t tmpRegSize = (p->curr.execWidth == 8) ? elemNum * 2 : elemNum;
> const GenRegister dst = ra->genReg(insn.dst(tmpRegSize));
> @@ -365,7 +365,7 @@ namespace gbe
> const GenRegister src = ra->genReg(insn.src(0));
> const GenRegister tempAddr = ra->genReg(insn.src(1));
> const uint32_t bti = insn.extra.function;
> - p->READ_FLOAT64(dst, tmp, tempAddr, src, bti, elemNum);
> + p->READ64(dst, tmp, tempAddr, src, bti, elemNum);
> }
>
> void GenContext::emitUntypedReadInstruction(const SelectionInstruction &insn) {
> @@ -379,13 +379,13 @@ namespace gbe
> // For SIMD8, we allocate 2*elemNum temporary registers from dst(0), and
> // then follow the real destination registers.
> // For SIMD16, we allocate elemNum temporary registers from dst(0).
> - void GenContext::emitWriteFloat64Instruction(const SelectionInstruction &insn) {
> + void GenContext::emitWrite64Instruction(const SelectionInstruction &insn) {
> const GenRegister src = ra->genReg(insn.src(0));
> const uint32_t elemNum = insn.extra.elem;
> const uint32_t tmpRegSize = (p->curr.execWidth == 8) ? elemNum * 2 : elemNum;
> const GenRegister data = ra->genReg(insn.src(tmpRegSize + 1));
> const uint32_t bti = insn.extra.function;
> - p->WRITE_FLOAT64(src, data, bti, elemNum);
> + p->WRITE64(src, data, bti, elemNum);
> }
>
> void GenContext::emitUntypedWriteInstruction(const SelectionInstruction &insn) {
> diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
> index 5dfaef9..82d41b6 100644
> --- a/backend/src/backend/gen_context.hpp
> +++ b/backend/src/backend/gen_context.hpp
> @@ -87,8 +87,8 @@ namespace gbe
> void emitBarrierInstruction(const SelectionInstruction &insn);
> void emitFenceInstruction(const SelectionInstruction &insn);
> void emitMathInstruction(const SelectionInstruction &insn);
> - void emitReadFloat64Instruction(const SelectionInstruction &insn);
> - void emitWriteFloat64Instruction(const SelectionInstruction &insn);
> + void emitRead64Instruction(const SelectionInstruction &insn);
> + void emitWrite64Instruction(const SelectionInstruction &insn);
> void emitUntypedReadInstruction(const SelectionInstruction &insn);
> void emitUntypedWriteInstruction(const SelectionInstruction &insn);
> void emitAtomicInstruction(const SelectionInstruction &insn);
> diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
> index b2be32f..70e542f 100644
> --- a/backend/src/backend/gen_encoder.cpp
> +++ b/backend/src/backend/gen_encoder.cpp
> @@ -356,7 +356,7 @@ namespace gbe
> 0
> };
>
> - void GenEncoder::READ_FLOAT64(GenRegister dst, GenRegister tmp, GenRegister addr, GenRegister src, uint32_t bti, uint32_t elemNum) {
> + void GenEncoder::READ64(GenRegister dst, GenRegister tmp, GenRegister addr, GenRegister src, uint32_t bti, uint32_t elemNum) {
> GenRegister dst32 = GenRegister::retype(dst, GEN_TYPE_UD);
> src = GenRegister::retype(src, GEN_TYPE_UD);
> addr = GenRegister::retype(addr, GEN_TYPE_UD);
> @@ -390,7 +390,7 @@ namespace gbe
> pop();
> }
>
> - void GenEncoder::WRITE_FLOAT64(GenRegister msg, GenRegister data, uint32_t bti, uint32_t elemNum) {
> + void GenEncoder::WRITE64(GenRegister msg, GenRegister data, uint32_t bti, uint32_t elemNum) {
> GenRegister data32 = GenRegister::retype(data, GEN_TYPE_UD);
> msg = GenRegister::retype(msg, GEN_TYPE_UD);
> int originSimdWidth = curr.execWidth;
> diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
> index 86e1a71..054c343 100644
> --- a/backend/src/backend/gen_encoder.hpp
> +++ b/backend/src/backend/gen_encoder.hpp
> @@ -142,10 +142,10 @@ namespace gbe
> void WAIT(void);
> /*! Atomic instructions */
> void ATOMIC(GenRegister dst, uint32_t function, GenRegister src, uint32_t bti, uint32_t srcNum);
> - /*! Read 64-bits float arrays */
> - void READ_FLOAT64(GenRegister dst, GenRegister tmp, GenRegister addr, GenRegister src, uint32_t bti, uint32_t elemNum);
> - /*! Write 64-bits float arrays */
> - void WRITE_FLOAT64(GenRegister src, GenRegister data, uint32_t bti, uint32_t elemNum);
> + /*! Read 64-bits float/int arrays */
> + void READ64(GenRegister dst, GenRegister tmp, GenRegister addr, GenRegister src, uint32_t bti, uint32_t elemNum);
> + /*! Write 64-bits float/int arrays */
> + void WRITE64(GenRegister src, GenRegister data, uint32_t bti, uint32_t elemNum);
> /*! Untyped read (upto 4 channels) */
> void UNTYPED_READ(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum);
> /*! Untyped write (upto 4 channels) */
> diff --git a/backend/src/backend/gen_insn_gen7_schedule_info.hxx b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
> index f3f4a25..6f37c3d 100644
> --- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
> +++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
> @@ -12,8 +12,8 @@ DECL_GEN7_SCHEDULE(Wait, 20, 2, 2)
> DECL_GEN7_SCHEDULE(Math, 20, 4, 2)
> DECL_GEN7_SCHEDULE(Barrier, 80, 1, 1)
> DECL_GEN7_SCHEDULE(Fence, 80, 1, 1)
> -DECL_GEN7_SCHEDULE(ReadFloat64, 80, 1, 1)
> -DECL_GEN7_SCHEDULE(WriteFloat64, 80, 1, 1)
> +DECL_GEN7_SCHEDULE(Read64, 80, 1, 1)
> +DECL_GEN7_SCHEDULE(Write64, 80, 1, 1)
> DECL_GEN7_SCHEDULE(UntypedRead, 80, 1, 1)
> DECL_GEN7_SCHEDULE(UntypedWrite, 80, 1, 1)
> DECL_GEN7_SCHEDULE(ByteGather, 80, 1, 1)
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 83d9b00..f3baa6d 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -167,14 +167,14 @@ namespace gbe
>
> bool SelectionInstruction::isRead(void) const {
> return this->opcode == SEL_OP_UNTYPED_READ ||
> - this->opcode == SEL_OP_READ_FLOAT64 ||
> + this->opcode == SEL_OP_READ64 ||
> this->opcode == SEL_OP_ATOMIC ||
> this->opcode == SEL_OP_BYTE_GATHER;
> }
>
> bool SelectionInstruction::isWrite(void) const {
> return this->opcode == SEL_OP_UNTYPED_WRITE ||
> - this->opcode == SEL_OP_WRITE_FLOAT64 ||
> + this->opcode == SEL_OP_WRITE64 ||
> this->opcode == SEL_OP_ATOMIC ||
> this->opcode == SEL_OP_BYTE_SCATTER;
> }
> @@ -465,10 +465,10 @@ namespace gbe
> void WAIT(void);
> /*! Atomic instruction */
> void ATOMIC(Reg dst, uint32_t function, uint32_t srcNum, Reg src0, Reg src1, Reg src2, uint32_t bti);
> - /*! Read 64 bits float array */
> - void READ_FLOAT64(Reg addr, Reg tempAddr, const GenRegister *dst, uint32_t elemNum, uint32_t valueNum, uint32_t bti);
> - /*! Write 64 bits float array */
> - void WRITE_FLOAT64(Reg addr, const GenRegister *src, uint32_t elemNum, uint32_t valueNum, uint32_t bti);
> + /*! Read 64 bits float/int array */
> + void READ64(Reg addr, Reg tempAddr, const GenRegister *dst, uint32_t elemNum, uint32_t valueNum, uint32_t bti);
> + /*! Write 64 bits float/int array */
> + void WRITE64(Reg addr, const GenRegister *src, uint32_t elemNum, uint32_t valueNum, uint32_t bti);
> /*! Untyped read (up to 4 elements) */
> void UNTYPED_READ(Reg addr, const GenRegister *dst, uint32_t elemNum, uint32_t bti);
> /*! Untyped write (up to 4 elements) */
> @@ -762,14 +762,14 @@ namespace gbe
>
> /* elemNum contains all the temporary register and the
> real destination registers.*/
> - void Selection::Opaque::READ_FLOAT64(Reg addr,
> + void Selection::Opaque::READ64(Reg addr,
> Reg tempAddr,
> const GenRegister *dst,
> uint32_t elemNum,
> uint32_t valueNum,
> uint32_t bti)
> {
> - SelectionInstruction *insn = this->appendInsn(SEL_OP_READ_FLOAT64, elemNum, 2);
> + SelectionInstruction *insn = this->appendInsn(SEL_OP_READ64, elemNum, 2);
> SelectionVector *srcVector = this->appendVector();
> SelectionVector *dstVector = this->appendVector();
>
> @@ -821,13 +821,13 @@ namespace gbe
>
> /* elemNum contains all the temporary register and the
> real data registers.*/
> - void Selection::Opaque::WRITE_FLOAT64(Reg addr,
> + void Selection::Opaque::WRITE64(Reg addr,
> const GenRegister *src,
> uint32_t elemNum,
> uint32_t valueNum,
> uint32_t bti)
> {
> - SelectionInstruction *insn = this->appendInsn(SEL_OP_WRITE_FLOAT64, 0, elemNum+1);
> + SelectionInstruction *insn = this->appendInsn(SEL_OP_WRITE64, 0, elemNum+1);
> SelectionVector *vector = this->appendVector();
>
> // Regular instruction to encode
> @@ -1840,6 +1840,8 @@ namespace gbe
> using namespace ir;
> switch (type) {
> case TYPE_DOUBLE:
> + case TYPE_S64:
> + case TYPE_U64:
> return GEN_BYTE_SCATTER_QWORD;
> case TYPE_FLOAT:
> case TYPE_U32:
> @@ -1872,7 +1874,7 @@ namespace gbe
> sel.UNTYPED_READ(addr, dst.data(), valueNum, bti);
> }
>
> - void emitReadFloat64(Selection::Opaque &sel,
> + void emitRead64(Selection::Opaque &sel,
> const ir::LoadInstruction &insn,
> GenRegister addr,
> uint32_t bti) const
> @@ -1890,7 +1892,7 @@ namespace gbe
> dst[dstID] = sel.selReg(sel.reg(FAMILY_DWORD));
> for ( uint32_t valueID = 0; valueID < valueNum; ++dstID, ++valueID)
> dst[dstID] = sel.selReg(insn.getValue(valueID));
> - sel.READ_FLOAT64(addr, sel.selReg(sel.reg(FAMILY_QWORD)), dst, valueNum + tmpRegNum, valueNum, bti);
> + sel.READ64(addr, sel.selReg(sel.reg(FAMILY_QWORD)), dst, valueNum + tmpRegNum, valueNum, bti);
> }
>
> void emitByteGather(Selection::Opaque &sel,
> @@ -1945,7 +1947,7 @@ namespace gbe
> if (insn.getAddressSpace() == MEM_CONSTANT)
> this->emitIndirectMove(sel, insn, address);
> else if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_QWORD)
> - this->emitReadFloat64(sel, insn, address, space == MEM_LOCAL ? 0xfe : 0x00);
> + this->emitRead64(sel, insn, address, space == MEM_LOCAL ? 0xfe : 0x00);
> else if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_DWORD)
> this->emitUntypedRead(sel, insn, address, space == MEM_LOCAL ? 0xfe : 0x00);
> else {
> @@ -1976,7 +1978,7 @@ namespace gbe
> sel.UNTYPED_WRITE(addr, value.data(), valueNum, bti);
> }
>
> - void emitWriteFloat64(Selection::Opaque &sel,
> + void emitWrite64(Selection::Opaque &sel,
> const ir::StoreInstruction &insn,
> uint32_t bti) const
> {
> @@ -1996,7 +1998,7 @@ namespace gbe
>
> for (uint32_t valueID = 0; valueID < valueNum; ++srcID, ++valueID)
> src[srcID] = sel.selReg(insn.getValue(valueID));
> - sel.WRITE_FLOAT64(addr, src, valueNum + tmpRegNum, valueNum, bti);
> + sel.WRITE64(addr, src, valueNum + tmpRegNum, valueNum, bti);
> }
>
> void emitByteScatter(Selection::Opaque &sel,
> @@ -2029,7 +2031,7 @@ namespace gbe
> const Type type = insn.getValueType();
> const uint32_t elemSize = getByteScatterGatherSize(type);
> if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_QWORD)
> - this->emitWriteFloat64(sel, insn, bti);
> + this->emitWrite64(sel, insn, bti);
> else if (insn.isAligned() == true && elemSize == GEN_BYTE_SCATTER_DWORD)
> this->emitUntypedWrite(sel, insn, bti);
> else {
> diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
> index 33c3937..c6aede5 100644
> --- a/backend/src/backend/gen_insn_selection.hxx
> +++ b/backend/src/backend/gen_insn_selection.hxx
> @@ -35,8 +35,8 @@ DECL_SELECTION_IR(BARRIER, BarrierInstruction)
> DECL_SELECTION_IR(FENCE, FenceInstruction)
> DECL_SELECTION_IR(UNTYPED_READ, UntypedReadInstruction)
> DECL_SELECTION_IR(UNTYPED_WRITE, UntypedWriteInstruction)
> -DECL_SELECTION_IR(READ_FLOAT64, ReadFloat64Instruction)
> -DECL_SELECTION_IR(WRITE_FLOAT64, WriteFloat64Instruction)
> +DECL_SELECTION_IR(READ64, Read64Instruction)
> +DECL_SELECTION_IR(WRITE64, Write64Instruction)
> DECL_SELECTION_IR(BYTE_GATHER, ByteGatherInstruction)
> DECL_SELECTION_IR(BYTE_SCATTER, ByteScatterInstruction)
> DECL_SELECTION_IR(SAMPLE, SampleInstruction)
> diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
> index 34df8d7..2589848 100644
> --- a/backend/src/ir/instruction.cpp
> +++ b/backend/src/ir/instruction.cpp
> @@ -664,6 +664,7 @@ namespace ir {
> static const Type allButBool[] = {TYPE_S8, TYPE_U8,
> TYPE_S16, TYPE_U16,
> TYPE_S32, TYPE_U32,
> + TYPE_S64, TYPE_U64,
> TYPE_FLOAT, TYPE_DOUBLE};
> static const uint32_t allButBoolNum = ARRAY_ELEM_NUM(allButBool);
>
> --
> 1.8.1.2
>
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