[Beignet] [PATCH 1/2] support 64bit-integer selection operator "?:"

[Zhigang Gong]

One comment here, we don't need to add a new MOV_INT64 instruction here.
We could reuse the original MOV easily. Please look at the function alu1
in gen_encoder.cpp, and do the following change, should be enough.

  INLINE void alu1(GenEncoder *p, uint32_t opcode, GenRegister dst, GenRegister src) {
-     if (dst.isdf() && src.isdf()) {
+     if (((dst.isdf() && src.isdf()) && (dst.isint64() && src.isint64()))
       handleDouble(p, opcode, dst, src);
     } else if (needToSplitAlu1(p, dst, src) == false) {

Any thoughts?

On Wed, Aug 07, 2013 at 03:01:04PM +0800, Homer Hsing wrote:
> Signed-off-by: Homer Hsing <homer.xing at intel.com>
> ---
>  backend/src/backend/gen_context.cpp        | 36 ++++++++++++++++++++++++++++++
>  backend/src/backend/gen_insn_selection.cpp | 12 ++++++++--
>  backend/src/backend/gen_insn_selection.hxx |  2 ++
>  3 files changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
> index ec73459..570e1f0 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -139,6 +139,23 @@ namespace gbe
>      const GenRegister src = ra->genReg(insn.src(0));
>      switch (insn.opcode) {
>        case SEL_OP_MOV: p->MOV(dst, src); break;
> +      case SEL_OP_MOV_INT64:
> +        {
> +          GenRegister xdst = GenRegister::retype(dst, GEN_TYPE_UL),
> +                      xsrc = GenRegister::retype(src, GEN_TYPE_UL);
> +          int execWidth = p->curr.execWidth;
> +          p->push();
> +          p->curr.execWidth = 8;
> +          for (int nib = 0; nib < execWidth / 4; nib ++) {
> +            p->curr.chooseNib(nib);
> +            p->MOV(xdst.bottom_half(), xsrc.bottom_half());
> +            p->MOV(xdst.top_half(), xsrc.top_half());
> +            xdst = GenRegister::suboffset(xdst, 4);
> +            xsrc = GenRegister::suboffset(xsrc, 4);
> +          }
> +          p->pop();
> +        }
> +        break;
>        case SEL_OP_FBH: p->FBH(dst, src); break;
>        case SEL_OP_FBL: p->FBL(dst, src); break;
>        case SEL_OP_NOT: p->NOT(dst, src); break;
> @@ -159,6 +176,25 @@ namespace gbe
>        case SEL_OP_LOAD_DF_IMM: p->LOAD_DF_IMM(dst, src1, src0.value.df); break;
>        case SEL_OP_MOV_DF: p->MOV_DF(dst, src0, src1); break;
>        case SEL_OP_SEL:  p->SEL(dst, src0, src1); break;
> +      case SEL_OP_SEL_INT64:
> +        {
> +          GenRegister xdst = GenRegister::retype(dst, GEN_TYPE_UL),
> +                      xsrc0 = GenRegister::retype(src0, GEN_TYPE_UL),
> +                      xsrc1 = GenRegister::retype(src1, GEN_TYPE_UL);
> +          int execWidth = p->curr.execWidth;
> +          p->push();
> +          p->curr.execWidth = 8;
> +          for (int nib = 0; nib < execWidth / 4; nib ++) {
> +            p->curr.chooseNib(nib);
> +            p->SEL(xdst.bottom_half(), xsrc0.bottom_half(), xsrc1.bottom_half());
> +            p->SEL(xdst.top_half(), xsrc0.top_half(), xsrc1.top_half());
> +            xdst = GenRegister::suboffset(xdst, 4);
> +            xsrc0 = GenRegister::suboffset(xsrc0, 4);
> +            xsrc1 = GenRegister::suboffset(xsrc1, 4);
> +          }
> +          p->pop();
> +        }
> +        break;
>        case SEL_OP_AND:  p->AND(dst, src0, src1); break;
>        case SEL_OP_OR:   p->OR (dst, src0, src1);  break;
>        case SEL_OP_XOR:  p->XOR(dst, src0, src1); break;
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 7e9402d..6cc012e 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -414,11 +414,13 @@ namespace gbe
>    INLINE void OP(Reg dst, Reg src0, Reg src1, Reg src2) { ALU3(SEL_OP_##OP, dst, src0, src1, src2); }
>      ALU1(MOV)
>      ALU2(MOV_DF)
> +    ALU1(MOV_INT64)
>      ALU2(LOAD_DF_IMM)
>      ALU1(LOAD_INT64_IMM)
>      ALU1(RNDZ)
>      ALU1(RNDE)
>      ALU2(SEL)
> +    ALU2(SEL_INT64)
>      ALU1(NOT)
>      ALU2(AND)
>      ALU2(OR)
> @@ -2247,11 +2249,17 @@ namespace gbe
>          sel.curr.physicalFlag = 0;
>          sel.curr.flagIndex = uint16_t(pred);
>          sel.curr.noMask = 0;
> -        sel.SEL(tmp, src0, src1);
> +        if(type == ir::TYPE_S64 || type == ir::TYPE_U64)
> +          sel.SEL_INT64(tmp, src0, src1);
> +        else
> +          sel.SEL(tmp, src0, src1);
>        sel.pop();
>  
>        // Update the destination register properly now
> -      sel.MOV(dst, tmp);
> +      if(type == ir::TYPE_S64 || type == ir::TYPE_U64)
> +        sel.MOV_INT64(dst, tmp);
> +      else
> +        sel.MOV(dst, tmp);
>        return true;
>      }
>    };
> diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
> index 7664c8f..d2e9db3 100644
> --- a/backend/src/backend/gen_insn_selection.hxx
> +++ b/backend/src/backend/gen_insn_selection.hxx
> @@ -1,6 +1,7 @@
>  DECL_SELECTION_IR(LABEL, LabelInstruction)
>  DECL_SELECTION_IR(MOV, UnaryInstruction)
>  DECL_SELECTION_IR(MOV_DF, BinaryInstruction)
> +DECL_SELECTION_IR(MOV_INT64, UnaryInstruction)
>  DECL_SELECTION_IR(LOAD_DF_IMM, BinaryInstruction)
>  DECL_SELECTION_IR(LOAD_INT64_IMM, UnaryInstruction)
>  DECL_SELECTION_IR(NOT, UnaryInstruction)
> @@ -11,6 +12,7 @@ DECL_SELECTION_IR(RNDD, UnaryInstruction)
>  DECL_SELECTION_IR(RNDU, UnaryInstruction)
>  DECL_SELECTION_IR(FRC, UnaryInstruction)
>  DECL_SELECTION_IR(SEL, BinaryInstruction)
> +DECL_SELECTION_IR(SEL_INT64, BinaryInstruction)
>  DECL_SELECTION_IR(AND, BinaryInstruction)
>  DECL_SELECTION_IR(OR, BinaryInstruction)
>  DECL_SELECTION_IR(XOR, BinaryInstruction)
> -- 
> 1.8.1.2
> 
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