[Beignet] [PATCH] GBE: don't use flag register as src 1 for xor instruction.

[Zhigang Gong]

Gen doesn't support to use ARF as src1. This bug is reported by
Edward Ching <edward.k.ching at gmail.com>.

Signed-off-by: Zhigang Gong <zhigang.gong at linux.intel.com>
---
 backend/src/backend/gen_reg_allocation.cpp |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index a765917..0bb75a2 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -645,7 +645,8 @@ namespace gbe
 
         // Flag registers can only go to src[0]
         const SelectionOpcode opcode = SelectionOpcode(insn.opcode);
-        if (opcode == SEL_OP_AND || opcode == SEL_OP_OR) {
+        if (opcode == SEL_OP_AND || opcode == SEL_OP_OR || opcode == SEL_OP_XOR
+            || opcode == SEL_OP_I64AND || opcode == SEL_OP_I64OR || opcode == SEL_OP_I64XOR) {
           if (insn.src(1).physical == 0) {
             const ir::Register reg = insn.src(1).reg();
             if (ctx.sel->getRegisterFamily(reg) == ir::FAMILY_BOOL)
-- 
1.7.9.5