[Beignet] [PATCH v2] Fix int div/rem assert in SIMD8 mode.

[Zhigang Gong]

Pushed, thanks.

On Wed, May 29, 2013 at 10:09:38AM +0800, Yang Rong wrote:
> 
> Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> ---
>  backend/src/backend/gen_encoder.cpp |   39 ++++++++++++++++++-----------------
>  1 file changed, 20 insertions(+), 19 deletions(-)
> 
> diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
> index d6c34fb..b65cc94 100644
> --- a/backend/src/backend/gen_encoder.cpp
> +++ b/backend/src/backend/gen_encoder.cpp
> @@ -1,4 +1,4 @@
> -/* 
> +/*
>   * Copyright © 2012 Intel Corporation
>   *
>   * This library is free software; you can redistribute it and/or
> @@ -21,7 +21,7 @@
>   Copyright (C) Intel Corp.  2006.  All Rights Reserved.
>   Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
>   develop this 3D driver.
> - 
> +
>   Permission is hereby granted, free of charge, to any person obtaining
>   a copy of this software and associated documentation files (the
>   "Software"), to deal in the Software without restriction, including
> @@ -29,11 +29,11 @@
>   distribute, sublicense, and/or sell copies of the Software, and to
>   permit persons to whom the Software is furnished to do so, subject to
>   the following conditions:
> - 
> +
>   The above copyright notice and this permission notice (including the
>   next paragraph) shall be included in all copies or substantial
>   portions of the Software.
> - 
> +
>   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
> @@ -41,7 +41,7 @@
>   LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
>   OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
>   WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> - 
> +
>   **********************************************************************/
>   /*
>    * Authors:
> @@ -334,7 +334,7 @@ namespace gbe
>           insn->bits3.da16.src1_reg_nr = reg.nr;
>         }
>  
> -       if (reg.width == GEN_WIDTH_1 && 
> +       if (reg.width == GEN_WIDTH_1 &&
>             insn->header.execution_size == GEN_WIDTH_1) {
>           insn->bits3.da1.src1_horiz_stride = GEN_HORIZONTAL_STRIDE_0;
>           insn->bits3.da1.src1_width = GEN_WIDTH_1;
> @@ -802,20 +802,21 @@ namespace gbe
>  
>       if (function == GEN_MATH_FUNCTION_INT_DIV_QUOTIENT ||
>           function == GEN_MATH_FUNCTION_INT_DIV_REMAINDER) {
> -        assert(insn->header.execution_size == GEN_WIDTH_16);
> -        insn->header.execution_size = GEN_WIDTH_8;
> +        if(insn->header.execution_size == GEN_WIDTH_16) {
> +          GenInstruction *insn2 = this->next(GEN_OPCODE_MATH);
> +          GenRegister new_dest, new_src0, new_src1;
> +          new_dest = GenRegister::QnPhysical(dst, 1);
> +          new_src0 = GenRegister::QnPhysical(src0, 1);
> +          new_src1 = GenRegister::QnPhysical(src1, 1);
> +          insn2->header.destreg_or_condmod = function;
> +          this->setHeader(insn2);
> +          insn2->header.execution_size = GEN_WIDTH_8;
> +          this->setDst(insn2, new_dest);
> +          this->setSrc0(insn2, new_src0);
> +          this->setSrc1(insn2, new_src1);
> +        }
>  
> -        GenInstruction *insn2 = this->next(GEN_OPCODE_MATH);
> -        GenRegister new_dest, new_src0, new_src1;
> -        new_dest = GenRegister::QnPhysical(dst, 1);
> -        new_src0 = GenRegister::QnPhysical(src0, 1);
> -        new_src1 = GenRegister::QnPhysical(src1, 1);
> -        insn2->header.destreg_or_condmod = function;
> -        this->setHeader(insn2);
> -        insn2->header.execution_size = GEN_WIDTH_8;
> -        this->setDst(insn2, new_dest);
> -        this->setSrc0(insn2, new_src0);
> -        this->setSrc1(insn2, new_src1);
> +        insn->header.execution_size = GEN_WIDTH_8;
>       }
>    }
>  
> -- 
> 1.7.9.5
> 
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