[Beignet] [PATCH] fix 64bit writing

[Homer Hsing]

fix 64bit writing when data register is scalar
this patch make some piglit test case pass

Signed-off-by: Homer Hsing <homer.xing at intel.com>
---
 backend/src/backend/gen_context.cpp |  2 +-
 backend/src/backend/gen_encoder.cpp | 17 ++++++++++++++---
 backend/src/backend/gen_encoder.hpp |  2 +-
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 949ef2d..6864a14 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -1494,7 +1494,7 @@ namespace gbe
     const GenRegister data = ra->genReg(insn.src(1));
     const uint32_t bti = insn.extra.function;
     p->MOV(src, addr);
-    p->WRITE64(src, data, bti, elemNum);
+    p->WRITE64(src, data, bti, elemNum, isScalarReg(data.reg()));
   }
 
   void GenContext::emitUntypedWriteInstruction(const SelectionInstruction &insn) {
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index abd5050..50dfd43 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -405,8 +405,9 @@ namespace gbe
     pop();
   }
 
-  void GenEncoder::WRITE64(GenRegister msg, GenRegister data, uint32_t bti, uint32_t elemNum) {
+  void GenEncoder::WRITE64(GenRegister msg, GenRegister data, uint32_t bti, uint32_t elemNum, bool is_scalar) {
     GenRegister data32 = GenRegister::retype(data, GEN_TYPE_UD);
+    GenRegister unpacked;
     msg = GenRegister::retype(msg, GEN_TYPE_UD);
     int originSimdWidth = curr.execWidth;
     int originPredicate = curr.predicate;
@@ -416,9 +417,19 @@ namespace gbe
       curr.predicate = GEN_PREDICATE_NONE;
       curr.noMask = GEN_MASK_DISABLE;
       curr.execWidth = 8;
-      MOV(GenRegister::suboffset(msg, originSimdWidth), GenRegister::unpacked_ud(data32.nr, data32.subnr + half));
+      if (is_scalar) {
+        unpacked = data32;
+        unpacked.subnr += half * 4;
+      } else
+        unpacked = GenRegister::unpacked_ud(data32.nr, data32.subnr + half);
+      MOV(GenRegister::suboffset(msg, originSimdWidth), unpacked);
       if (originSimdWidth == 16) {
-        MOV(GenRegister::suboffset(msg, originSimdWidth + 8), GenRegister::unpacked_ud(data32.nr + 2, data32.subnr + half));
+        if (is_scalar) {
+          unpacked = data32;
+          unpacked.subnr += half * 4;
+        } else
+          unpacked = GenRegister::unpacked_ud(data32.nr + 2, data32.subnr + half);
+        MOV(GenRegister::suboffset(msg, originSimdWidth + 8), unpacked);
         curr.execWidth = 16;
       }
       if (half == 1)
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index fe5245e..d518c4a 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -147,7 +147,7 @@ namespace gbe
     /*! Read 64-bits float/int arrays */
     void READ64(GenRegister dst, GenRegister tmp, GenRegister addr, GenRegister src, uint32_t bti, uint32_t elemNum);
     /*! Write 64-bits float/int arrays */
-    void WRITE64(GenRegister src, GenRegister data, uint32_t bti, uint32_t elemNum);
+    void WRITE64(GenRegister src, GenRegister data, uint32_t bti, uint32_t elemNum, bool is_scalar);
     /*! Untyped read (upto 4 channels) */
     void UNTYPED_READ(GenRegister dst, GenRegister src, uint32_t bti, uint32_t elemNum);
     /*! Untyped write (upto 4 channels) */
-- 
1.8.1.2