[Beignet] [PATCH V2 1/2] GBE: Use varying register to save one instruction

Zhigang Gong zhigang.gong at linux.intel.com
Mon Jul 14 18:08:40 PDT 2014


LGTM, pushed, thanks.

On Mon, Jul 14, 2014 at 05:24:37PM +0800, Yang Rong wrote:
> From: Ruiling Song <ruiling.song at intel.com>
> 
> Signed-off-by: Ruiling Song <ruiling.song at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp |    3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index fb041de..cd2240d 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -2787,12 +2787,11 @@ namespace gbe
>          GBE_ASSERT(elemSize == GEN_BYTE_SCATTER_WORD || elemSize == GEN_BYTE_SCATTER_BYTE);
>  
>          Register tmpReg = sel.reg(FAMILY_DWORD, simdWidth == 1);
> -        GenRegister tmpAddr = GenRegister::udxgrf(simdWidth, sel.reg(FAMILY_DWORD, simdWidth == 1));
> +        GenRegister tmpAddr = GenRegister::udxgrf(simdWidth, sel.reg(FAMILY_DWORD));
>          GenRegister tmpData = GenRegister::udxgrf(simdWidth, tmpReg);
>          // Get dword aligned addr
>          sel.push();
>            if (simdWidth == 1) {
> -            sel.curr.execWidth = 1;
>              sel.curr.noMask = 1;
>            }
>            sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UD), GenRegister::immud(0xfffffffc));
> -- 
> 1.7.10.4
> 
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