[Beignet] [PATCH] GBE: fix unpacked_uw/ub on uniform registers.
Song, Ruiling
ruiling.song at intel.com
Mon May 19 01:08:21 PDT 2014
Looks good to me.
-----Original Message-----
From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of Zhigang Gong
Sent: Wednesday, May 14, 2014 10:48 AM
To: beignet at lists.freedesktop.org
Cc: Gong, Zhigang
Subject: [Beignet] [PATCH] GBE: fix unpacked_uw/ub on uniform registers.
unpacked_uw/ub macros hard coded the register's width to 8 which is bad for uniform registers. This patch fix that issue.
Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
backend/src/backend/gen_insn_selection.cpp | 28 ++++++++++++++++++----------
backend/src/backend/gen_register.hpp | 16 ++++++++--------
2 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 0cb633f..adf523c 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -321,6 +321,14 @@ namespace gbe
const ir::RegisterData ®Data = getRegisterData(reg);
return regData.isUniform();
}
+
+ INLINE GenRegister unpacked_uw(const ir::Register ®) const {
+ return GenRegister::unpacked_uw(reg, isScalarReg(reg));
+ }
+
+ INLINE GenRegister unpacked_ub(const ir::Register ®) const {
+ return GenRegister::unpacked_ub(reg, isScalarReg(reg));
+ }
/*! Implement public class */
INLINE uint32_t getRegNum(void) const { return file.regNum(); }
/*! Implements public interface */
@@ -1866,7 +1874,7 @@ namespace gbe
//bytes and shorts must be converted to int for DIV and REM per GEN restriction
if((family == FAMILY_WORD || family == FAMILY_BYTE)) {
GenRegister tmp0, tmp1;
- ir::Register reg = sel.reg(FAMILY_DWORD);
+ ir::Register reg = sel.reg(FAMILY_DWORD, simdWidth == 1);
tmp0 = GenRegister::udxgrf(simdWidth, reg);
tmp0 = GenRegister::retype(tmp0, GEN_TYPE_D); @@ -1879,9 +1887,9 @@ namespace gbe
sel.MATH(tmp0, function, tmp0, tmp1);
GenRegister unpacked;
if(family == FAMILY_WORD) {
- unpacked = GenRegister::unpacked_uw(reg);
+ unpacked = sel.unpacked_uw(reg);
} else {
- unpacked = GenRegister::unpacked_ub(reg);
+ unpacked = sel.unpacked_ub(reg);
}
unpacked = GenRegister::retype(unpacked, getGenType(type));
sel.MOV(dst, unpacked);
@@ -2704,9 +2712,9 @@ namespace gbe
sel.SHR(tmpData, tmpData, tmpAddr);
if (elemSize == GEN_BYTE_SCATTER_WORD)
- sel.MOV(GenRegister::retype(value, GEN_TYPE_UW), GenRegister::unpacked_uw(tmpReg));
+ sel.MOV(GenRegister::retype(value, GEN_TYPE_UW),
+ sel.unpacked_uw(tmpReg));
else if (elemSize == GEN_BYTE_SCATTER_BYTE)
- sel.MOV(GenRegister::retype(value, GEN_TYPE_UB), GenRegister::unpacked_ub(tmpReg));
+ sel.MOV(GenRegister::retype(value, GEN_TYPE_UB),
+ sel.unpacked_ub(tmpReg));
sel.pop();
}
}
@@ -2998,10 +3006,10 @@ namespace gbe
}
if(wideReg.hstride != GEN_VERTICAL_STRIDE_0) {
if(multiple == 2) {
- wideReg = GenRegister::unpacked_uw(wideReg.reg());
+ wideReg = sel.unpacked_uw(wideReg.reg());
wideReg = GenRegister::retype(wideReg, getGenType(narrowType));
} else if(multiple == 4) {
- wideReg = GenRegister::unpacked_ub(wideReg.reg());
+ wideReg = sel.unpacked_ub(wideReg.reg());
wideReg = GenRegister::retype(wideReg, getGenType(narrowType));
} else if(multiple == 8) { //need to specail handle long to char
GBE_ASSERT(multiple == 8);
@@ -3064,18 +3072,18 @@ namespace gbe
sel.F16TO32(dst, src);
} else if (opcode == OP_F32TO16) {
GenRegister unpacked;
- unpacked = GenRegister::unpacked_uw(sel.reg(FAMILY_DWORD));
+ unpacked = sel.unpacked_uw(sel.reg(FAMILY_DWORD,
+ sel.isScalarReg(insn.getSrc(0))));
sel.F32TO16(unpacked, src);
sel.MOV(dst, unpacked);
} else if (dstFamily != FAMILY_DWORD && dstFamily != FAMILY_QWORD && (srcFamily == FAMILY_DWORD || srcFamily == FAMILY_QWORD)) {
GenRegister unpacked;
if (dstFamily == FAMILY_WORD) {
const uint32_t type = dstType == TYPE_U16 ? GEN_TYPE_UW : GEN_TYPE_W;
- unpacked = GenRegister::unpacked_uw(sel.reg(FAMILY_DWORD));
+ unpacked = sel.unpacked_uw(sel.reg(FAMILY_DWORD,
+ sel.isScalarReg(insn.getSrc(0))));
unpacked = GenRegister::retype(unpacked, type);
} else {
const uint32_t type = dstType == TYPE_U8 ? GEN_TYPE_UB : GEN_TYPE_B;
- unpacked = GenRegister::unpacked_ub(sel.reg(FAMILY_DWORD));
+ unpacked = sel.unpacked_ub(sel.reg(FAMILY_DWORD,
+ sel.isScalarReg(insn.getSrc(0))));
unpacked = GenRegister::retype(unpacked, type);
}
if(srcFamily == FAMILY_QWORD) { diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp
index 6863aab..50a6dcd 100644
--- a/backend/src/backend/gen_register.hpp
+++ b/backend/src/backend/gen_register.hpp
@@ -491,22 +491,22 @@ namespace gbe
return retype(vec1(file, reg), GEN_TYPE_UB);
}
- static INLINE GenRegister unpacked_uw(ir::Register reg) {
+ static INLINE GenRegister unpacked_uw(ir::Register reg, bool
+ uniform = false) {
return GenRegister(GEN_GENERAL_REGISTER_FILE,
reg,
GEN_TYPE_UW,
- GEN_VERTICAL_STRIDE_16,
- GEN_WIDTH_8,
- GEN_HORIZONTAL_STRIDE_2);
+ uniform ? GEN_VERTICAL_STRIDE_0 : GEN_VERTICAL_STRIDE_16,
+ uniform ? GEN_WIDTH_1 : GEN_WIDTH_8,
+ uniform ? GEN_HORIZONTAL_STRIDE_0 :
+ GEN_HORIZONTAL_STRIDE_2);
}
- static INLINE GenRegister unpacked_ub(ir::Register reg) {
+ static INLINE GenRegister unpacked_ub(ir::Register reg, bool
+ uniform = false) {
return GenRegister(GEN_GENERAL_REGISTER_FILE,
reg,
GEN_TYPE_UB,
- GEN_VERTICAL_STRIDE_32,
- GEN_WIDTH_8,
- GEN_HORIZONTAL_STRIDE_4);
+ uniform ? GEN_VERTICAL_STRIDE_0 : GEN_VERTICAL_STRIDE_32,
+ uniform ? GEN_WIDTH_1 : GEN_WIDTH_8,
+ uniform ? GEN_HORIZONTAL_STRIDE_0 :
+ GEN_HORIZONTAL_STRIDE_4);
}
static INLINE GenRegister imm(uint32_t type) {
--
1.8.3.2
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