[Beignet] [PATCH 0/5] post scheduling and preparation for mix simd16 to simd8 mode.

[Zhigang Gong]

To support simd16/9 mixing, we have to do two things:
1. collect IR layer vector information and pass it into register allocation function
   to allocate proper contiguous regions for those ir vectors.
2. Enable post register allocation instruction scheduling, as we need to do the instruction
   merging after register allocation.

This patch set finish the above two things, and do some optimization on the
post instruction scheduling. This patchset itself could get about 10% performance
improvement with luxmark.

Zhigang Gong (5):
  GBE: disable mad for some cases.
  GBE: fix one post register allocation instruction scheduling bug.
  GBE: optimize post reg allocation instruction scheduling.
  GBE: fix post scheduling related bug for spill/unspill.
  GBE: preparation to mix simd16 into simd8 kernel.

 .../src/backend/gen_insn_gen7_schedule_info.hxx    |  48 ++--
 backend/src/backend/gen_insn_scheduling.cpp        | 262 ++++++++++++++-------
 backend/src/backend/gen_insn_selection.cpp         |  98 ++++++--
 backend/src/backend/gen_insn_selection.hpp         |  44 +++-
 backend/src/backend/gen_reg_allocation.cpp         | 103 +++++---
 backend/src/ir/function.hpp                        |  25 ++
 backend/src/ir/unit.cpp                            |   1 +
 backend/src/ir/unit.hpp                            |  39 +++
 backend/src/llvm/llvm_gen_backend.cpp              |  14 +-
 backend/src/llvm/llvm_gen_backend.hpp              |   3 +-
 backend/src/llvm/llvm_scalarize.cpp                |  13 +-
 backend/src/llvm/llvm_to_gen.cpp                   |   2 +-
 12 files changed, 481 insertions(+), 171 deletions(-)

-- 
1.8.3.2