[Beignet] [PATCH] GBE: fix one illegal instruction when replace a uniform dst.

[Zhigang Gong]

Please ignore this version, forgot to add the src(0) assignment for
non 1 simdWidth. Will send a new version soon.

On Thu, May 29, 2014 at 12:30:26PM +0800, Zhigang Gong wrote:
> When the dst is a uniform value, we replace it with a vector value, then
> copy the vector value back may generate an illegal instruction as below
> at address 18:
> 
>     (14      )  mov(16)         g124<1>:F       g127.7<0,1,0>:F                 { align1 WE_all 1H };
>     (16      )  send(16)        g122<1>:UW      g124<8,8,1>:UD
>                 data (bti: 1, rgba: 14, SIMD16, legacy, Untyped Surface Read) mlen 2 rlen 2 { align1 WE_all 1H };
>     (18      )  mov(1)          g127.6<1>:F     g122<8,8,1>:F                   { align1 WE_all };
> 
> This patch could fix this issue and generate correct instruction as below:
> 
>     (      14)  mov(16)         g124<1>:UD      g127.7<0,1,0>:UD                { align1 WE_all 1H };
>     (      16)  send(16)        g122<1>:UW      g124<8,8,1>:UD
>                 data (bti: 1, rgba: 14, SIMD16, legacy, Untyped Surface Read) mlen 2 rlen 2 { align1 WE_all 1H };
>     (      18)  mov(1)          g127.6<1>:UD    g122<0,1,0>:UD                  { align1 WE_all };
> 
> Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 9886357..c3bae0d 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -945,9 +945,10 @@ namespace gbe
>        SelectionInstruction *mov = this->create(SEL_OP_MOV, 1, 1);
>        mov->dst(0) = GenRegister::retype(insn->dst(regID), gr.type);
>        mov->state = GenInstructionState(simdWidth);
> -      if (simdWidth == 1)
> +      if (simdWidth == 1) {
>          mov->state.noMask = 1;
> -      mov->src(0) = gr;
> +        mov->src(0) = GenRegister::retype(GenRegister::vec1(GEN_GENERAL_REGISTER_FILE, gr.reg()), gr.type);
> +      }
>        insn->append(*mov);
>      }
>      insn->dst(regID) = gr;
> -- 
> 1.8.3.2
> 
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