[Beignet] [PATCH 3/4] GBE: one minor bug in OP_SIMD_XXX.

[Yang, Rong R]

Hi,

    For NullaryInstruction, how to decide the dst is uniform or not?

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Zhigang Gong
> Sent: Thursday, August 13, 2015 10:24
> To: beignet at lists.freedesktop.org
> Cc: Gong, Zhigang
> Subject: [Beignet] [PATCH 3/4] GBE: one minor bug in OP_SIMD_XXX.
> 
> Need to take care of the uniform cases.
> 
> Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp
> b/backend/src/backend/gen_insn_selection.cpp
> index b84bb4b..1ddf3e9 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -2314,10 +2314,16 @@ namespace gbe
>        GenRegister dst = sel.selReg(insn.getDst(0), type);
> 
>        sel.push();
> +      if (sel.isScalarReg(insn.getDst(0))) {
> +        sel.curr.execWidth = 1;
> +        sel.curr.predicate = GEN_PREDICATE_NONE;
> +        sel.curr.noMask = 1;
> +      }
> +
>        switch (opcode) {
>          case ir::OP_SIMD_SIZE:
>            {
> -            const GenRegister src = GenRegister::immud(sel.curr.execWidth);
> +            const GenRegister src = GenRegister::immud(sel.ctx.getSimdWidth());
>              sel.MOV(dst, src);
>            }
>            break;
> --
> 1.9.1
> 
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