[Beignet] [PATCH] correct simd width when dst of simd_shuffle is scalar

[Yang, Rong R]

LGTM.

Maybe we can move the scalar check to low level in some common place to avoid forgot.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Guo Yejun
> Sent: Wednesday, August 26, 2015 02:51
> To: beignet at lists.freedesktop.org
> Cc: Guo, Yejun
> Subject: [Beignet] [PATCH] correct simd width when dst of simd_shuffle is
> scalar
> 
> originally, the dst of simd_shuffle is not uniform, but if it is optimized as scalar,
> just use simd_width=1 to generate sel_op/asm
> 
> Signed-off-by: Guo Yejun <yejun.guo at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp
> b/backend/src/backend/gen_insn_selection.cpp
> index b84bb4b..b0a7f57 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -5022,6 +5022,11 @@ namespace gbe
>        }
> 
>        sel.push();
> +      if (sel.isScalarReg(insn.getDst(0))) {
> +        sel.curr.execWidth = 1;
> +        sel.curr.predicate = GEN_PREDICATE_NONE;
> +        sel.curr.noMask = 1;
> +      }
>        if (src1.file == GEN_IMMEDIATE_VALUE)
>          sel.SIMD_SHUFFLE(dst, src0, src1);
>        else {
> --
> 1.9.1
> 
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