[Beignet] [PATCH 2/5] GBE: refine liveness analysis.

[Zhigang Gong]

Only in gen backend stage, we need to take care of the
special extra liveout and uniform analysis. In IR stage,
we don't need to handle them.

Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
 backend/src/backend/context.cpp |  2 +-
 backend/src/ir/liveness.cpp     | 17 ++++++++++-------
 backend/src/ir/liveness.hpp     |  2 +-
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/backend/src/backend/context.cpp b/backend/src/backend/context.cpp
index 33b2409..81b284d 100644
--- a/backend/src/backend/context.cpp
+++ b/backend/src/backend/context.cpp
@@ -322,7 +322,7 @@ namespace gbe
     unit(unit), fn(*unit.getFunction(name)), name(name), liveness(NULL), dag(NULL), useDWLabel(false)
   {
     GBE_ASSERT(unit.getPointerSize() == ir::POINTER_32_BITS);
-    this->liveness = GBE_NEW(ir::Liveness, const_cast<ir::Function&>(fn));
+    this->liveness = GBE_NEW(ir::Liveness, const_cast<ir::Function&>(fn), true);
     this->dag = GBE_NEW(ir::FunctionDAG, *this->liveness);
     // r0 (GEN_REG_SIZE) is always set by the HW and used at the end by EOT
     this->registerAllocator = NULL; //GBE_NEW(RegisterAllocator, GEN_REG_SIZE, 4*KB - GEN_REG_SIZE);
diff --git a/backend/src/ir/liveness.cpp b/backend/src/ir/liveness.cpp
index 9fa7ac3..e2240c0 100644
--- a/backend/src/ir/liveness.cpp
+++ b/backend/src/ir/liveness.cpp
@@ -27,7 +27,7 @@
 namespace gbe {
 namespace ir {
 
-  Liveness::Liveness(Function &fn) : fn(fn) {
+  Liveness::Liveness(Function &fn, bool isInGenBackend) : fn(fn) {
     // Initialize UEVar and VarKill for each block
     fn.foreachBlock([this](const BasicBlock &bb) {
       this->initBlock(bb);
@@ -48,12 +48,15 @@ namespace ir {
     }
     // extend register (def in loop, use out-of-loop) liveness to the whole loop
     set<Register> extentRegs;
-    this->computeExtraLiveInOut(extentRegs);
-    // analyze uniform values. The extentRegs contains all the values which is
-    // defined in a loop and use out-of-loop which could not be a uniform. The reason
-    // is that when it reenter the second time, it may active different lanes. So
-    // reenter many times may cause it has different values in different lanes.
-    this->analyzeUniform(&extentRegs);
+    // Only in Gen backend we need to take care of extra live out analysis.
+    if (isInGenBackend) {
+      this->computeExtraLiveInOut(extentRegs);
+      // analyze uniform values. The extentRegs contains all the values which is
+      // defined in a loop and use out-of-loop which could not be a uniform. The reason
+      // is that when it reenter the second time, it may active different lanes. So
+      // reenter many times may cause it has different values in different lanes.
+      this->analyzeUniform(&extentRegs);
+    }
   }
 
   Liveness::~Liveness(void) {
diff --git a/backend/src/ir/liveness.hpp b/backend/src/ir/liveness.hpp
index 4a7dc4e..d9fa2ed 100644
--- a/backend/src/ir/liveness.hpp
+++ b/backend/src/ir/liveness.hpp
@@ -48,7 +48,7 @@ namespace ir {
   class Liveness : public NonCopyable
   {
   public:
-    Liveness(Function &fn);
+    Liveness(Function &fn, bool isInGenBackend = false);
     ~Liveness(void);
     /*! Set of variables used upwards in the block (before a definition) */
     typedef set<Register> UEVar;
-- 
1.9.1