[Beignet] [PATCH 2/3] Add Indirect struct argument read support.

[Zhigang Gong]

On Mon, May 11, 2015 at 02:02:53PM +0800, Yang Rong wrote:
> The steps to handle Indirect argument read:
> 1. Find out all indirect loads and its address caculation.
> 2. Add INDIRECT_MOV IR instruction, replace load to INDIRECT_MOV.
> 3. Replace the bass address and offset ADD instruction to offset MOV instruction. Could optimize.
> 
> Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> ---
>  backend/src/backend/gen_context.cpp        |  31 +++++--
>  backend/src/backend/gen_insn_selection.cpp |  45 +++++----
>  backend/src/backend/gen_insn_selection.hpp |   1 +
>  backend/src/backend/gen_register.hpp       |  11 ++-
>  backend/src/ir/instruction.cpp             |  50 ++++++++++
>  backend/src/ir/instruction.hpp             |  10 ++
>  backend/src/ir/instruction.hxx             |   1 +
>  backend/src/ir/lowering.cpp                | 141 +++++++++++++++++++++++++++--
>  8 files changed, 254 insertions(+), 36 deletions(-)
> 
> diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
> index 62fd596..1d1dc40 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -1695,21 +1695,32 @@ namespace gbe
>    }
>  
>    void GenContext::emitIndirectMoveInstruction(const SelectionInstruction &insn) {
> -    GenRegister src = ra->genReg(insn.src(0));
> -    if(sel->isScalarReg(src.reg()))
> -      src = GenRegister::retype(src, GEN_TYPE_UW);
> -    else
> -      src = GenRegister::unpacked_uw(src.nr, src.subnr / typeSize(GEN_TYPE_UW));
> +    GenRegister baseReg = ra->genReg(insn.src(0));
> +    GenRegister offset = GenRegister::retype(ra->genReg(insn.src(1)), GEN_TYPE_UW);
> +    uint32_t immoffset = insn.extra.indirect_offset;
>  
>      const GenRegister dst = ra->genReg(insn.dst(0));
>      const GenRegister a0 = GenRegister::addr8(0);
>      uint32_t simdWidth = p->curr.execWidth;
> +    GenRegister indirect_src;
> +
> +    if(sel->isScalarReg(offset.reg()))
> +      offset = GenRegister::retype(offset, GEN_TYPE_UW);
> +    else
> +      offset = GenRegister::unpacked_uw(offset.nr, offset.subnr / typeSize(GEN_TYPE_UW));
> +    uint32_t baseRegOffset = GenRegister::grfOffset(baseReg);
> +    //There is a restrict that: lower 5 bits indirect reg SubRegNum and
> +    //the lower 5 bits of indirect imm SubRegNum cannot exceed 5 bits.
> +    //So can't use AddrImm field, need a add.
> +    p->ADD(offset, offset, GenRegister::immuw(baseRegOffset + immoffset));
We should not use offset as destination here, as this offset may be reused latter.
Should use a temporary register here. The other part LGTM.

Thanks,
Zhigang Gong.