[Beignet] [PATCH] add more OP for LOGICAL_SRCMOD case

[Yang, Rong R]

LGTM, thanks.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Guo Yejun
> Sent: Friday, October 23, 2015 3:27
> To: beignet at lists.freedesktop.org
> Cc: Guo, Yejun
> Subject: [Beignet] [PATCH] add more OP for LOGICAL_SRCMOD case
> 
> currently, only OP_ADD is considered, actually, from hw spec, and, not, or,
> xor 's srcmod are all logical
> 
> Signed-off-by: Guo Yejun <yejun.guo at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp          | 6 +++---
>  backend/src/backend/gen_insn_selection.hpp          | 6 +++---
>  backend/src/backend/gen_insn_selection_optimize.cpp | 5 +++--
>  3 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp
> b/backend/src/backend/gen_insn_selection.cpp
> index 6833457..02212e1 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -2131,7 +2131,7 @@ namespace gbe
>      this->opaque->setHasLongType(true);
>      this->opaque->setSlowByteGather(true);
>      this->opaque->setHasHalfType(true);
> -    opt_features = SIOF_OP_AND_LOGICAL_SRCMOD;
> +    opt_features = SIOF_LOGICAL_SRCMOD;
>    }
> 
>    SelectionChv::SelectionChv(GenContext &ctx) : Selection(ctx) { @@ -2140,7
> +2140,7 @@ namespace gbe
>      this->opaque->setLongRegRestrict(true);
>      this->opaque->setSlowByteGather(true);
>      this->opaque->setHasHalfType(true);
> -    opt_features = SIOF_OP_AND_LOGICAL_SRCMOD |
> SIOF_OP_MOV_LONG_REG_RESTRICT;
> +    opt_features = SIOF_LOGICAL_SRCMOD |
> SIOF_OP_MOV_LONG_REG_RESTRICT;
>    }
> 
>    Selection9::Selection9(GenContext &ctx) : Selection(ctx) { @@ -2149,7
> +2149,7 @@ namespace gbe
>      this->opaque->setLdMsgOrder(LD_MSG_ORDER_SKL);
>      this->opaque->setSlowByteGather(true);
>      this->opaque->setHasHalfType(true);
> -    opt_features = SIOF_OP_AND_LOGICAL_SRCMOD;
> +    opt_features = SIOF_LOGICAL_SRCMOD;
>    }
> 
>    void Selection::Opaque::TYPED_WRITE(GenRegister *msgs, uint32_t
> msgNum, diff --git a/backend/src/backend/gen_insn_selection.hpp
> b/backend/src/backend/gen_insn_selection.hpp
> index 4efb80b..f51c905 100644
> --- a/backend/src/backend/gen_insn_selection.hpp
> +++ b/backend/src/backend/gen_insn_selection.hpp
> @@ -227,9 +227,9 @@ namespace gbe
>    };
> 
>    enum SEL_IR_OPT_FEATURE {
> -    //for OP_AND, on BDW+, SrcMod value indicates a logical source modifier
> -    //            on PRE-BDW, SrcMod value indicates a numeric source modifier
> -    SIOF_OP_AND_LOGICAL_SRCMOD = 1 << 0,
> +    //for OP_AND/not/or/xor , on BDW+, SrcMod value indicates a logical
> source modifier
> +    //                        on PRE-BDW, SrcMod value indicates a numeric source
> modifier
> +    SIOF_LOGICAL_SRCMOD = 1 << 0,
>      //for OP_MOV, on BSW, for long data type, src and dst hstride must be
> aligned to the same qword
>      SIOF_OP_MOV_LONG_REG_RESTRICT = 1 << 1,
>    };
> diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp
> b/backend/src/backend/gen_insn_selection_optimize.cpp
> index fffc8b0..81405ba 100644
> --- a/backend/src/backend/gen_insn_selection_optimize.cpp
> +++ b/backend/src/backend/gen_insn_selection_optimize.cpp
> @@ -170,8 +170,9 @@ namespace gbe
>      if (insn.isWrite() || insn.isRead()) //register in selection vector
>        return false;
> 
> -    if (features & SIOF_OP_AND_LOGICAL_SRCMOD)
> -      if (insn.opcode == SEL_OP_AND && (info->replacement.absolute || info-
> >replacement.negation))
> +    if (features & SIOF_LOGICAL_SRCMOD)
> +      if ((insn.opcode == SEL_OP_AND || insn.opcode == SEL_OP_NOT ||
> insn.opcode == SEL_OP_OR || insn.opcode == SEL_OP_XOR) &&
> +            (info->replacement.absolute || info->replacement.negation))
>          return false;
> 
>      if (features & SIOF_OP_MOV_LONG_REG_RESTRICT && insn.opcode ==
> SEL_OP_MOV) {
> --
> 1.9.1
> 
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