[Beignet] [PATCH 3/7] pass dbginfo from gen ir to geninsn
He Junyan
junyan.he at inbox.com
Thu Oct 8 07:27:56 PDT 2015
On Fri, Sep 18, 2015 at 05:01:53PM +0800, Bai Yannan wrote:
> Date: Fri, 18 Sep 2015 17:01:53 +0800
> From: Bai Yannan <yannan.bai at intel.com>
> To: beignet at lists.freedesktop.org
> Cc: Bai Yannan <yannan.bai at intel.com>
> Subject: [Beignet] [PATCH 3/7] pass dbginfo from gen ir to geninsn
> X-Mailer: git-send-email 1.9.1
>
> 1, pass debug infomation first from gen ir to selection ir;
> 2, pass debug infomation from selection ir to gen instruction;
> 3, print line and column binded with ASM into a log file.
>
> Signed-off-by: Bai Yannan <yannan.bai at intel.com>
> ---
> backend/src/backend/gen_context.cpp | 54 +++++++++++++++++++
> backend/src/backend/gen_defs.hpp | 4 ++
> backend/src/backend/gen_encoder.cpp | 15 ++++++
> backend/src/backend/gen_encoder.hpp | 4 ++
> backend/src/backend/gen_insn_selection.cpp | 84 +++++++++++++++++++++++++++++-
> backend/src/backend/gen_insn_selection.hpp | 7 +++
> 6 files changed, 167 insertions(+), 1 deletion(-)
>
> diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
> index 25fdf08..411336e 100644
> --- a/backend/src/backend/gen_context.cpp
> +++ b/backend/src/backend/gen_context.cpp
> @@ -91,6 +91,11 @@ namespace gbe
> return i;
> }
>
> +#define SET_GENINSN_DBGINFO(INSN) \
> + if(INSN.dbginfo.hasdbginfo) \
> + p->setDbginfo(INSN.dbginfo.line,INSN.dbginfo.col);\
> + else p->setDbginfo(0,0)
> +
> void GenContext::emitInstructionStream(void) {
> // Emit Gen ISA
> for (auto &block : *sel->blockList)
> @@ -106,12 +111,14 @@ namespace gbe
> #include "backend/gen_insn_selection.hxx"
> #undef DECL_INSN
> }
> + //p->setDbginfo(insn.dbginfo.line,insn.dbginfo.col);
> p->pop();
> }
> /* per spec, pad the instruction stream with 8 nop to avoid
> instruction prefetcher prefetch into an invalide page */
> for(int i = 0; i < 8; i++)
> p->NOP();
> + p->setDbginfo(0,0);
> }
>
> bool GenContext::patchBranches(void) {
> @@ -241,6 +248,7 @@ namespace gbe
> p->curr.execWidth = this->simdWidth;
> p->ADD(stackptr, stackptr, GenRegister::ud1grf(126,0));
> p->pop();
> + //SET_GENINSN_DBGINFO(0);
> }
>
> void GenContext::emitLabelInstruction(const SelectionInstruction &insn) {
> @@ -320,6 +328,7 @@ namespace gbe
> break;
> default: NOT_IMPLEMENTED;
> }
> + SET_GENINSN_DBGINFO(insn);
I think that SET_GENINSN_DBGINFO should be add to a common place like in instruction.cpp.
> }
>
> void GenContext::emitUnaryWithTempInstruction(const SelectionInstruction &insn) {
> @@ -478,6 +487,7 @@ namespace gbe
> default:
> NOT_IMPLEMENTED;
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitBinaryWithTempInstruction(const SelectionInstruction &insn) {
> @@ -578,6 +588,7 @@ namespace gbe
> default:
> NOT_IMPLEMENTED;
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitSimdShuffleInstruction(const SelectionInstruction &insn) {
> @@ -620,6 +631,10 @@ namespace gbe
> const GenRegister dst = ra->genReg(insn.dst(0));
> const GenRegister src0 = ra->genReg(insn.src(0));
> const GenRegister src1 = ra->genReg(insn.src(1));
> + // debug
> + if(insn.dbginfo.hasdbginfo)
> + std::cout<<" *** "<<insn.dbginfo.line<<std::endl;
> +
> switch (insn.opcode) {
> case SEL_OP_SEL: p->SEL(dst, src0, src1); break;
> case SEL_OP_SEL_INT64:
> @@ -668,6 +683,7 @@ namespace gbe
> break;
> default: NOT_IMPLEMENTED;
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::collectShifter(GenRegister dest, GenRegister src) {
> @@ -762,6 +778,7 @@ namespace gbe
> }
> storeTopHalf(dest, e);
> storeBottomHalf(dest, f);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64MADSATInstruction(const SelectionInstruction &insn) {
> @@ -893,6 +910,7 @@ namespace gbe
> }
> storeTopHalf(dest, g);
> storeBottomHalf(dest, h);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64HADDInstruction(const SelectionInstruction &insn) {
> @@ -920,6 +938,7 @@ namespace gbe
> p->OR(c, c, d);
> storeBottomHalf(dest, a);
> storeTopHalf(dest, c);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64RHADDInstruction(const SelectionInstruction &insn) {
> @@ -950,6 +969,7 @@ namespace gbe
> p->OR(c, c, d);
> storeBottomHalf(dest, a);
> storeTopHalf(dest, c);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64ShiftInstruction(const SelectionInstruction &insn) {
> @@ -1056,6 +1076,7 @@ namespace gbe
> default:
> NOT_IMPLEMENTED;
> }
> + SET_GENINSN_DBGINFO(insn);
> }
> void GenContext::setFlag(GenRegister flagReg, GenRegister src) {
> p->push();
> @@ -1211,6 +1232,7 @@ namespace gbe
> p->OR(dest, dest, GenRegister::immud(0x80000000));
> p->pop();
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
>
> @@ -1250,6 +1272,7 @@ namespace gbe
> }
> storeTopHalf(dst, high);
> storeBottomHalf(dst, low);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64CompareInstruction(const SelectionInstruction &insn) {
> @@ -1330,6 +1353,7 @@ namespace gbe
> p->curr.execWidth = 1;
> p->MOV(GenRegister::flag(flag, subFlag), f1);
> p->pop();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64SATADDInstruction(const SelectionInstruction &insn) {
> @@ -1379,6 +1403,7 @@ namespace gbe
> p->pop();
> storeTopHalf(dst, a);
> storeBottomHalf(dst, b);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64SATSUBInstruction(const SelectionInstruction &insn) {
> @@ -1427,6 +1452,7 @@ namespace gbe
> p->pop();
> storeTopHalf(dst, a);
> storeBottomHalf(dst, b);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::loadTopHalf(GenRegister dest, GenRegister src) {
> @@ -1524,6 +1550,7 @@ namespace gbe
> p->pop();
> storeTopHalf(dest, e);
> storeBottomHalf(dest, a);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitI64DIVREMInstruction(const SelectionInstruction &insn) {
> @@ -1677,6 +1704,7 @@ namespace gbe
> storeTopHalf(dest, a);
> storeBottomHalf(dest, b);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitTernaryInstruction(const SelectionInstruction &insn) {
> @@ -1688,14 +1716,17 @@ namespace gbe
> case SEL_OP_MAD: p->MAD(dst, src0, src1, src2); break;
> default: NOT_IMPLEMENTED;
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitNoOpInstruction(const SelectionInstruction &insn) {
> p->NOP();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitWaitInstruction(const SelectionInstruction &insn) {
> p->WAIT();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitBarrierInstruction(const SelectionInstruction &insn) {
> @@ -1722,12 +1753,14 @@ namespace gbe
> // Now we wait for the other threads
> p->WAIT();
> p->pop();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitFenceInstruction(const SelectionInstruction &insn) {
> const GenRegister dst = ra->genReg(insn.dst(0));
> p->FENCE(dst);
> p->MOV(dst, dst);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitMathInstruction(const SelectionInstruction &insn) {
> @@ -1739,6 +1772,7 @@ namespace gbe
> p->MATH(dst, function, src0, src1);
> } else
> p->MATH(dst, function, src0);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitCompareInstruction(const SelectionInstruction &insn) {
> @@ -1752,6 +1786,7 @@ namespace gbe
> const GenRegister dst = ra->genReg(insn.dst(0));
> p->SEL_CMP(insn.extra.function, dst, src0, src1);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitAtomicInstruction(const SelectionInstruction &insn) {
> @@ -1777,6 +1812,7 @@ namespace gbe
> p->pop();
> afterMessage(insn, bti, flagTemp, jip0);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitIndirectMoveInstruction(const SelectionInstruction &insn) {
> @@ -1820,6 +1856,7 @@ namespace gbe
> p->MOV(nextDst, indirect_src);
> p->pop();
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::insertJumpPos(const SelectionInstruction &insn) {
> @@ -1831,6 +1868,7 @@ namespace gbe
> insertJumpPos(insn);
> const GenRegister src = ra->genReg(insn.src(0));
> p->JMPI(src, insn.extra.longjmp);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitEotInstruction(const SelectionInstruction &insn) {
> @@ -1841,6 +1879,7 @@ namespace gbe
> p->curr.execWidth = 8;
> p->EOT(112);
> p->pop();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitSpillRegInstruction(const SelectionInstruction &insn) {
> @@ -1877,6 +1916,7 @@ namespace gbe
> this->scratchWrite(msg, scratchOffset + 4*simdWidth, regNum, GEN_TYPE_UD, GEN_SCRATCH_CHANNEL_MODE_DWORD);
> }
> p->pop();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitUnSpillRegInstruction(const SelectionInstruction &insn) {
> @@ -1905,6 +1945,7 @@ namespace gbe
> storeTopHalf(dst, payload);
> }
> p->pop();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitRead64Instruction(const SelectionInstruction &insn) {
> @@ -1929,6 +1970,7 @@ namespace gbe
> p->pop();
> afterMessage(insn, bti, tmp, jip0);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
> unsigned GenContext::beforeMessage(const SelectionInstruction &insn, GenRegister bti, GenRegister tmp, unsigned desc) {
> const GenRegister flagReg = GenRegister::flag(insn.state.flag, insn.state.subFlag);
> @@ -1997,6 +2039,7 @@ namespace gbe
> p->pop();
> afterMessage(insn, bti, tmp, jip0);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitWrite64Instruction(const SelectionInstruction &insn) {
> @@ -2020,6 +2063,7 @@ namespace gbe
> p->pop();
> afterMessage(insn, bti, tmp, jip0);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitUntypedWriteInstruction(const SelectionInstruction &insn) {
> @@ -2042,6 +2086,7 @@ namespace gbe
> p->pop();
> afterMessage(insn, bti, tmp, jip0);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitByteGatherInstruction(const SelectionInstruction &insn) {
> @@ -2066,6 +2111,7 @@ namespace gbe
> p->pop();
> afterMessage(insn, bti, tmp, jip0);
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitByteScatterInstruction(const SelectionInstruction &insn) {
> @@ -2089,6 +2135,7 @@ namespace gbe
> p->pop();
> afterMessage(insn, bti, tmp, jip0);
> }
> + SET_GENINSN_DBGINFO(insn);
>
> }
>
> @@ -2097,6 +2144,7 @@ namespace gbe
> for(uint32_t i = 0; i < insn.dstNum; i++) {
> p->MOV(ra->genReg(insn.dst(i)), GenRegister::splitReg(src, insn.extra.elem, i));
> }
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitPackByteInstruction(const SelectionInstruction &insn) {
> @@ -2119,6 +2167,7 @@ namespace gbe
> }
> }
> p->pop();
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitUnpackLongInstruction(const SelectionInstruction &insn) {
> @@ -2134,6 +2183,7 @@ namespace gbe
> const GenRegister src = ra->genReg(insn.src(0));
> const uint32_t bti = insn.getbti();
> p->DWORD_GATHER(dst, src, bti);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::emitSampleInstruction(const SelectionInstruction &insn) {
> @@ -2144,6 +2194,7 @@ namespace gbe
> const unsigned int msgLen = insn.extra.rdmsglen;
> uint32_t simdWidth = p->curr.execWidth;
> p->SAMPLE(dst, msgPayload, msgLen, false, bti, sampler, simdWidth, -1, 0, insn.extra.isLD, insn.extra.isUniform);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::scratchWrite(const GenRegister header, uint32_t offset, uint32_t reg_num, uint32_t reg_type, uint32_t channel_mode) {
> @@ -2181,6 +2232,7 @@ namespace gbe
> const GenRegister header = GenRegister::retype(ra->genReg(insn.src(0)), GEN_TYPE_UD);
> const uint32_t bti = insn.getbti();
> p->TYPED_WRITE(header, true, bti);
> + SET_GENINSN_DBGINFO(insn);
> }
>
> void GenContext::setA0Content(uint16_t new_a0[16], uint16_t max_offset, int sz) {
> @@ -2351,6 +2403,8 @@ namespace gbe
> curLabel = (ir::LabelIndex)(curLabel + 1);
> }
> }
> + if (OCL_PROFILING)
> + fprintf(file, "[%3i,%3i]", p->storedbg[insnID].srcline, p->storedbg[insnID].srcline);
> fprintf(file, " (%8i) ", insnID);
> pCom = (GenCompactInstruction*)&p->store[insnID];
> if(pCom->bits1.cmpt_control == 1) {
> diff --git a/backend/src/backend/gen_defs.hpp b/backend/src/backend/gen_defs.hpp
> index 1ca148c..838056c 100644
> --- a/backend/src/backend/gen_defs.hpp
> +++ b/backend/src/backend/gen_defs.hpp
> @@ -471,6 +471,10 @@ enum GenMessageTarget {
> #define GEN_MAX_GRF 128
>
> /* Instruction format for the execution units */
> +struct GenInsnDBGInfo {
> + uint32_t srcline;
> + uint32_t srccol;
> +};
>
> struct GenInstruction {
> uint32_t low;
> diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
> index cac29e8..0f50c35 100644
> --- a/backend/src/backend/gen_encoder.cpp
> +++ b/backend/src/backend/gen_encoder.cpp
> @@ -50,6 +50,7 @@
>
> #include "backend/gen_encoder.hpp"
> #include <cstring>
> +#include <map>
>
>
> namespace gbe
> @@ -310,6 +311,7 @@ namespace gbe
> this->curr.subFlag = 0;
> this->curr.predicate = GEN_PREDICATE_NORMAL;
> this->curr.inversePredicate = 0;
> +// this->dbgnum = 0;
> }
>
> void GenEncoder::push(void) {
> @@ -1296,5 +1298,18 @@ namespace gbe
> insn->bits3.spawner_gen5.end_of_thread = 1;
> insn->header.destreg_or_condmod = GEN_SFID_THREAD_SPAWNER;
> }
> +
> + void GenEncoder::setDbginfo(uint32_t line,uint32_t col) {
> + GenInsnDBGInfo gd;
> + for(int i = 0; i<this->store.size(); i++)
> + {
> + auto it = this->storedbg.find(i);
> + if(it != this->storedbg.end())
> + continue;
> + gd.srcline = line;
> + gd.srccol = col;
> + storedbg[i] = gd;
> + }
> + }
> } /* namespace gbe */
>
> diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
> index 79e7b6e..9797abc 100644
> --- a/backend/src/backend/gen_encoder.hpp
> +++ b/backend/src/backend/gen_encoder.hpp
> @@ -57,6 +57,7 @@
> #include "sys/vector.hpp"
> #include <cassert>
> #include "src/cl_device_data.h"
> +#include <map>
>
> namespace gbe
> {
> @@ -256,6 +257,9 @@ namespace gbe
> GBE_CLASS(GenEncoder); //!< Use custom allocators
> virtual void alu3(uint32_t opcode, GenRegister dst,
> GenRegister src0, GenRegister src1, GenRegister src2) = 0;
> + public:
> + void setDbginfo(uint32_t line, uint32_t col);
> + std::map<int, GenInsnDBGInfo> storedbg;
> };
>
> void alu1(GenEncoder *p, uint32_t opcode, GenRegister dst,
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index ab00269..e861b7c 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -169,6 +169,9 @@ namespace gbe
> parent(NULL), opcode(op), dstNum(dst), srcNum(src)
> {
> extra.function = 0;
> + this->dbginfo.hasdbginfo = false;
> + this->dbginfo.line = 0;
> + this->dbginfo.col = 0;
> }
>
> void SelectionInstruction::prepend(SelectionInstruction &other) {
> @@ -455,6 +458,8 @@ namespace gbe
> bool hasQWord(const ir::Instruction &insn);
> /*! A root instruction needs to be generated */
> bool isRoot(const ir::Instruction &insn) const;
> + /*! Set debug infomation */
> + void setDbgInfo(uint32_t line, uint32_t col);
>
> /*! To handle selection block allocation */
> DECL_POOL(SelectionBlock, blockPool);
> @@ -1088,6 +1093,40 @@ namespace gbe
> return tmp;
> }
>
> +#define SET_SELINSN_DBGINFO(SELINSN) \
> +{ SELINSN.dbginfo.line = line; \
> + SELINSN.dbginfo.col = col; \
> + SELINSN.dbginfo.hasdbginfo = true;}
> +
> + void Selection::Opaque::setDbgInfo(uint32_t line, uint32_t col) {
> + if(this->bwdCodeGeneration)
> + for(auto it = this->bwdList.rbegin(); it!= this->bwdList.rend(); it++)
> + {
> + SelectionInstruction &selinsn = *it;
> + if(!selinsn.dbginfo.hasdbginfo)
> + //SET_SELINSN_DBGINFO(selinsn)
> + { selinsn.dbginfo.line = line;
> + selinsn.dbginfo.col = col;
> + selinsn.dbginfo.hasdbginfo = true;}
> + //else break;
> + }
> + else
> + for(auto it = this->blockList.rbegin(); it!= this->blockList.rend(); it++)
> + {
> + SelectionBlock &block = *it;
> + for(auto jt = block.insnList.rbegin(); jt!= block.insnList.rend(); jt++)
> + {
> + SelectionInstruction &selinsn = *jt;
> + if(!selinsn.dbginfo.hasdbginfo)
> + SET_SELINSN_DBGINFO(selinsn)
> + else goto OVER;
> + }
> + }
> + OVER:
> + ;
> + }
> +#undef SET_SELINSN_DBGINFO
> +
> #define SEL_REG(SIMD16, SIMD8, SIMD1) \
> if (ctx.sel->isScalarReg(reg) == true) \
> return GenRegister::retype(GenRegister::SIMD1(reg), genType); \
> @@ -1889,6 +1928,14 @@ namespace gbe
> // Build a selectionDAG node for instruction
> SelectionDAG *dag = this->newSelectionDAG(insn);
>
> + // debug
> + /*
> + std::cout<<dag->insn<<std::endl;
> + if((dag->insn).DBGInfo.line==0)
> + std::cout<<" N/A"<<std::endl;
> + else std::cout<<(dag->insn).DBGInfo.line<<"-----"<<std::endl<<std::endl;
> + */
> +
> // Point to non-root children
> const uint32_t srcNum = insn.getSrcNum();
> for (uint32_t srcID = 0; srcID < srcNum; ++srcID) {
> @@ -2289,6 +2336,12 @@ namespace gbe
> }
> };
>
> +#define OCL_PROFILING (bool)(getenv("OCL_PROFILING")[0]-48)
> +#define SET_SELOPAQUE_DBGINFO(INSN) \
> + if(OCL_PROFILING) \
> + if (INSN.DBGInfo.hasDBGInfo) \
> + sel.setDbgInfo(INSN.DBGInfo.line, INSN.DBGInfo.col)
> +
> /*! Declare a naive one-to-many pattern */
> #define DECL_PATTERN(FAMILY) \
> struct FAMILY##Pattern : public OneToManyPattern<FAMILY##Pattern, ir::FAMILY>
> @@ -2336,6 +2389,7 @@ namespace gbe
> default: NOT_SUPPORTED;
> }
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -2481,6 +2535,7 @@ namespace gbe
> default: NOT_SUPPORTED;
> }
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
> DECL_CTOR(UnaryInstruction, 1, 1)
> @@ -2582,6 +2637,7 @@ namespace gbe
> sel.pop();
> }
> markAllChildren(dag);
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
>
> @@ -2619,6 +2675,7 @@ namespace gbe
> }
> markAllChildren(dag);
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
>
> @@ -2857,6 +2914,7 @@ namespace gbe
> default: NOT_IMPLEMENTED;
> }
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -2910,6 +2968,7 @@ namespace gbe
> if (child0->child[0]) child0->child[0]->isRoot = 1;
> if (child0->child[1]) child0->child[1]->isRoot = 1;
> if (child1) child1->isRoot = 1;
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> if (child1 && child1->insn.getOpcode() == OP_MUL) {
> @@ -2928,6 +2987,7 @@ namespace gbe
> if (child1->child[0]) child1->child[0]->isRoot = 1;
> if (child1->child[1]) child1->child[1]->isRoot = 1;
> if (child0) child0->isRoot = 1;
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> return false;
> @@ -2990,6 +3050,7 @@ namespace gbe
> sel.curr.execWidth = simdWidth;
> sel.SEL_CMP(genCmp, dst, src0, src1);
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -3079,6 +3140,7 @@ namespace gbe
>
> // All children are marked as root
> markAllChildren(dag);
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -3131,6 +3193,7 @@ namespace gbe
> sel.pop();
> if (dag.child[childID ^ 1] != NULL)
> dag.child[childID ^ 1]->isRoot = 1;
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> if (type == TYPE_S32 && (imm.getIntegerValue() >= -32768 && imm.getIntegerValue() <= 32767)) {
> @@ -3147,6 +3210,7 @@ namespace gbe
> sel.pop();
> if (dag.child[childID ^ 1] != NULL)
> dag.child[childID ^ 1]->isRoot = 1;
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> }
> @@ -3174,6 +3238,7 @@ namespace gbe
> sel.selReg(src0, TYPE_U32));
> sel.pop();
> markAllChildren(dag);
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> return false;
> @@ -3256,6 +3321,7 @@ namespace gbe
> default: NOT_SUPPORTED;
> }
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
>
> @@ -3273,6 +3339,7 @@ namespace gbe
>
> // A barrier is OK to start the thread synchronization *and* SLM fence
> sel.BARRIER(GenRegister::ud8grf(reg), sel.selReg(sel.reg(FAMILY_DWORD)), params);
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
>
> @@ -3688,6 +3755,7 @@ namespace gbe
> dag.child[0] = NULL;
> markAllChildren(dag);
>
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -3834,6 +3902,7 @@ namespace gbe
> dag.child[0] = NULL;
> markAllChildren(dag);
>
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -3912,6 +3981,7 @@ namespace gbe
> sel.CMP(getGenCompare(opcode, inverseCmp), src0, src1, tmpDst);
> }
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -4075,6 +4145,7 @@ namespace gbe
>
> sel.pop();
>
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
> DECL_CTOR(BitCastInstruction, 1, 1);
> @@ -4569,6 +4640,7 @@ namespace gbe
> dag.child[0] = NULL;
> markAllChildren(dag);
>
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -4629,6 +4701,7 @@ namespace gbe
> sel.SEL(dst, src0, src1);
> sel.pop();
>
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -4675,6 +4748,7 @@ namespace gbe
> default:
> NOT_IMPLEMENTED;
> }
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
>
> @@ -4777,7 +4851,8 @@ namespace gbe
> }
> }
>
> - return true;
> + SET_SELOPAQUE_DBGINFO(insn);
> + return true;
> }
> DECL_CTOR(LabelInstruction, 1, 1);
> };
> @@ -4854,6 +4929,7 @@ namespace gbe
> uint32_t sampler = insn.getSamplerIndex();
>
> sel.SAMPLE(dst.data(), insn.getDstNum(), msgPayloads, msgLen, bti, sampler, insn.getSamplerOffset() != 0, false);
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
> DECL_CTOR(SampleInstruction, 1, 1);
> @@ -4942,6 +5018,7 @@ namespace gbe
> }
> sel.pop();
> }
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
> DECL_CTOR(TypedWriteInstruction, 1, 1);
> @@ -4958,6 +5035,7 @@ namespace gbe
> GenRegister imageInfoReg = GenRegister::ud1grf(insn.getSrc(0));
> sel.MOV(dst, imageInfoReg);
>
> + SET_SELOPAQUE_DBGINFO(insn);
> return true;
> }
> DECL_CTOR(GetImageInfoInstruction, 1, 1);
> @@ -4997,6 +5075,7 @@ namespace gbe
> GEN_WIDTH_8,
> GEN_HORIZONTAL_STRIDE_1));
> sel.pop();
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -5067,6 +5146,7 @@ namespace gbe
> sel.MOV(dst, src);
> sel.pop();
> markAllChildren(dag);
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -5090,6 +5170,7 @@ namespace gbe
>
> sel.INDIRECT_MOVE(dst, tmp, src0, src1, offset);
> markAllChildren(dag);
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
> };
> @@ -5284,6 +5365,7 @@ namespace gbe
> NOT_IMPLEMENTED;
>
> markAllChildren(dag);
> + SET_SELOPAQUE_DBGINFO(dag.insn);
> return true;
> }
>
> diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp
> index ffc79e1..581a70b 100644
> --- a/backend/src/backend/gen_insn_selection.hpp
> +++ b/backend/src/backend/gen_insn_selection.hpp
> @@ -145,6 +145,13 @@ namespace gbe
> uint32_t index1;
> /*! instruction ID used for vector allocation. */
> uint32_t ID;
> + /*! Debug infomation */
> + struct {
> + uint32_t line;
> + uint32_t col;
> + bool hasdbginfo;
> + } dbginfo;
> + //void setDbgInfo(uint32_t line, uint32_t col);s
> /*! Variable sized. Destinations and sources go here */
> GenRegister regs[0];
> INLINE uint32_t getbti() const {
> --
> 1.9.1
>
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