[Beignet] [PATCH] SKL: explicit disable media sampler DOP clock gate in PIPELINE_SELECT.

[Yang Rong]

This bit maybe enable by sbios, explicit disable to save power.

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 src/intel/intel_defines.h | 10 ++++++----
 src/intel/intel_gpgpu.c   |  3 ++-
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/intel/intel_defines.h b/src/intel/intel_defines.h
index 6ada30c..0c50fb9 100644
--- a/src/intel/intel_defines.h
+++ b/src/intel/intel_defines.h
@@ -85,10 +85,12 @@
 
 #define BASE_ADDRESS_MODIFY             (1 << 0)
 
-#define PIPELINE_SELECT_3D              0
-#define PIPELINE_SELECT_MEDIA           1
-#define PIPELINE_SELECT_GPGPU           2
-#define PIPELINE_SELECT_MASK            (3 << 8)
+#define PIPELINE_SELECT_3D               0
+#define PIPELINE_SELECT_MEDIA            1
+#define PIPELINE_SELECT_GPGPU            2
+#define PIPELINE_SELECT_DOP_GATE_DISABLE (0 << 4)
+#define PIPELINE_SELECT_MASK             (3 << 8)
+#define PIPELINE_SELECT_DOP_GATE_MASK    (1 << 12)
 
 #define UF0_CS_REALLOC                  (1 << 13)
 #define UF0_VFE_REALLOC                 (1 << 12)
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index 901bd98..8001ff4 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -259,7 +259,8 @@ static void
 intel_gpgpu_select_pipeline_gen9(intel_gpgpu_t *gpgpu)
 {
   BEGIN_BATCH(gpgpu->batch, 1);
-  OUT_BATCH(gpgpu->batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MASK | PIPELINE_SELECT_GPGPU);
+  OUT_BATCH(gpgpu->batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MASK | PIPELINE_SELECT_GPGPU |
+                          PIPELINE_SELECT_DOP_GATE_DISABLE | PIPELINE_SELECT_DOP_GATE_MASK);
   ADVANCE_BATCH(gpgpu->batch);
 }
 
-- 
1.8.3.2