[Bug 52256] KMS doesn't work with radeon HD 7520G

Sun Jul 22 16:27:27 PDT 2012

https://bugs.freedesktop.org/show_bug.cgi?id=52256

--- Comment #2 from LRN <lrn1986 at gmail.com> 2012-07-22 16:27:27 PDT ---
Here's a piece of syslog with drm debugging set to 0x04, and with some extra
lines of my own:

Jul 22 19:40:13 APC2 kernel: [   10.010370] [drm:radeon_dp_link_train_cr],
clock recovery at voltage 0 pre-emphasis 0
Jul 22 19:40:13 APC2 kernel: [   10.010550] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Using training pattern 2
Jul 22 19:40:13 APC2 kernel: [   10.010551] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Interval is 0, delaying for 400
Jul 22 19:40:13 APC2 kernel: [   10.012180] [drm:radeon_dp_get_link_status],
link status 01 00 80 00 04 00
Jul 22 19:40:13 APC2 kernel: [   10.012182] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: lane count = 1, lane align = 0x80; is & 0x1?
Jul 22 19:40:13 APC2 kernel: [   10.012184] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: Not done, return false
Jul 22 19:40:13 APC2 kernel: [   10.012184] [drm:dp_get_adjust_train],
requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB
Jul 22 19:40:13 APC2 kernel: [   10.012186] [drm:dp_get_adjust_train], using
signal parameters: voltage 0.4V pre_emph 3.5dB
Jul 22 19:40:13 APC2 kernel: [   10.013661] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Interval is 0, delaying for 400
Jul 22 19:40:13 APC2 kernel: [   10.015282] [drm:radeon_dp_get_link_status],
link status 01 00 80 00 08 00
Jul 22 19:40:13 APC2 kernel: [   10.015283] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: lane count = 1, lane align = 0x80; is & 0x1?
Jul 22 19:40:13 APC2 kernel: [   10.015285] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: Not done, return false
Jul 22 19:40:13 APC2 kernel: [   10.015285] [drm:dp_get_adjust_train],
requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB
Jul 22 19:40:13 APC2 kernel: [   10.015286] [drm:dp_get_adjust_train], using
signal parameters: voltage 0.4V pre_emph 6dB
Jul 22 19:40:13 APC2 kernel: [   10.016631] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Interval is 0, delaying for 400
Jul 22 19:40:13 APC2 kernel: [   10.018249] [drm:radeon_dp_get_link_status],
link status 01 00 80 00 0c 00
Jul 22 19:40:13 APC2 kernel: [   10.018250] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: lane count = 1, lane align = 0x80; is & 0x1?
Jul 22 19:40:13 APC2 kernel: [   10.018251] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: Not done, return false
Jul 22 19:40:13 APC2 kernel: [   10.018252] [drm:dp_get_adjust_train],
requested signal parameters: lane 0 voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.018253] [drm:dp_get_adjust_train], using
signal parameters: voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.019640] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Interval is 0, delaying for 400
Jul 22 19:40:13 APC2 kernel: [   10.021260] [drm:radeon_dp_get_link_status],
link status 01 00 80 00 0c 00
Jul 22 19:40:13 APC2 kernel: [   10.021262] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: lane count = 1, lane align = 0x80; is & 0x1?
Jul 22 19:40:13 APC2 kernel: [   10.021263] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: Not done, return false
Jul 22 19:40:13 APC2 kernel: [   10.021264] [drm:dp_get_adjust_train],
requested signal parameters: lane 0 voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.021265] [drm:dp_get_adjust_train], using
signal parameters: voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.022647] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Interval is 0, delaying for 400
Jul 22 19:40:13 APC2 kernel: [   10.024267] [drm:radeon_dp_get_link_status],
link status 01 00 80 00 0c 00
Jul 22 19:40:13 APC2 kernel: [   10.024269] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: lane count = 1, lane align = 0x80; is & 0x1?
Jul 22 19:40:13 APC2 kernel: [   10.024270] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: Not done, return false
Jul 22 19:40:13 APC2 kernel: [   10.024271] [drm:dp_get_adjust_train],
requested signal parameters: lane 0 voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.024272] [drm:dp_get_adjust_train], using
signal parameters: voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.025655] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Interval is 0, delaying for 400
Jul 22 19:40:13 APC2 kernel: [   10.027274] [drm:radeon_dp_get_link_status],
link status 01 00 80 00 0c 00
Jul 22 19:40:13 APC2 kernel: [   10.027276] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: lane count = 1, lane align = 0x80; is & 0x1?
Jul 22 19:40:13 APC2 kernel: [   10.027278] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: Not done, return false
Jul 22 19:40:13 APC2 kernel: [   10.027280] [drm:dp_get_adjust_train],
requested signal parameters: lane 0 voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.027281] [drm:dp_get_adjust_train], using
signal parameters: voltage 0.4V pre_emph 9.5dB
Jul 22 19:40:13 APC2 kernel: [   10.028659] [drm:radeon_dp_link_train_ce],
radeon_dp_link_train_ce: Interval is 0, delaying for 400
Jul 22 19:40:13 APC2 kernel: [   10.030279] [drm:radeon_dp_get_link_status],
link status 01 00 80 00 0c 00
Jul 22 19:40:13 APC2 kernel: [   10.030281] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: lane count = 1, lane align = 0x80; is & 0x1?
Jul 22 19:40:13 APC2 kernel: [   10.030282] [drm:dp_channel_eq_ok],
dp_channel_eq_ok: Not done, return false
Jul 22 19:40:13 APC2 kernel: [   10.030283] [drm:radeon_dp_link_train_ce]
*ERROR* channel eq failed: 5 tries
Jul 22 19:40:13 APC2 kernel: [   10.030284] [drm:radeon_dp_link_train_ce]
*ERROR* channel eq failed

#27314 mentions something similar. Well, at least link status looks more real
here than there. Anyway, the problem is in lack of DP alignment (whatever that
is...).

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