[PATCH 02/11 v3] drm/i915/intel_i2c: assign HDMI port D to pin pair 6
djkurtz at chromium.org
Mon Mar 26 10:49:51 PDT 2012
On Mon, Mar 26, 2012 at 11:08 PM, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Mon, Mar 26, 2012 at 04:47:11PM +0200, Daniel Vetter wrote:
> > On Mon, Mar 26, 2012 at 10:26:41PM +0800, Daniel Kurtz wrote:
> > > According to i915 documentation , "Port D" (DP/HDMI Port D) is
> > > actually gmbus pin pair 6 (gmbus0.2:0 == 110b GPIOF), not 7 (111b).
> > > Pin pair 7 is a reserved pair.
> > >
> > >  Documentation for [DevSNB+] and [DevIBX], as found on
> > > http://intellinuxgraphics.org
> > >
> > > Note: the "reserved" and "disabled" pairs do not actually map to a
> > > physical pair of pins, nor GPIO regs and shouldn't be initialized or
> > > used.
> > > Fixing this is left for a later patch.
> > >
> > > This bug has not been noticed for two reasons:
> > > 1) "gmbus" mode is currently disabled - all transfers are actually
> > > using
> > > "bit-bang" mode which uses the GPIO port 5 (the "HDMI/DPD
> > > CTLDATA/CLK"
> > > pair), at register 0x5024 (defined as GPIOF i915_reg.h).
> > > Since this is the correct pair of pins for HDMI1, transfers
> > > succeed.
> > ... this is no longer true on drm-intel-next.
> > > 2) Even if gmbus mode is re-enabled, the first attempted transaction
> > > will fail because it tries to use the wrong ("Reserved") pin pair.
> > > However, the driver immediately falls back again to the bit-bang
> > > method, which correctly uses GPIOF, so again, transfers succeed.
> > >
> > > However, if gmbus mode is re-enabled and the GPIO fall-back mode is
> > > disabled, then reading an attached monitor's EDID fail.
> > >
> > > Signed-off-by: Daniel Kurtz <djkurtz at chromium.org>
> > Otherwise this looks ok to me - I've checked with gen3 Bspec and we seem
> > to indeed have a 1:1 mapping, see "Display Registers", 1.5.3 "GPIO
> > Control
> > Registers", the list right below the heading.
> well, scrap that, I've confused myself here a bit. Afaict we don't
> actually use these gmbus ports on earlier chips.
> > Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > When resending, can you please add the Bspec reference above?
> Can you you instead add a clear reference (Volume, Full Section plus
> Heading Title) for the Snb/Ibx public Bspec.
> Thanks, Daneil
> Daniel Vetter
> Mail: daniel at ffwll.ch
> Mobile: +41 (0)79 365 57 48
I'm not sure what a "Bspec" is, but here is the documents I used:
Section 2.2.2 lists the 6 gmbus ports (gpio pin pairs):
[ 5: HDMI/DPD, 4: HDMIB, 3: HDMI/DPC, 2: LVDS, 1: SSC, 0: VGA ]
126.96.36.199 lists the GPIO registers to control these 6 ports.
188.8.131.52 lists the mapping between 5 of these gmbus ports and the 3
Pin_Pair_Select bits (of the GMBUS0 register). This table is missing
HDMIB (port 101).
Section 2.2.2 lists the same 6 gmbus ports plus two 'reserved' gpio ports.
184.108.40.206 lists 8 GPIO registers... however, it says the size of the
block is 6x32, which implies that those 2 reserved GPIO registers
(GPIO_6 & GPIO_7) don't actually exist (or are irrelevant).
220.127.116.11 lists the mapping between the 6 named gmbus ports and the 3
Pin_Pair_Select bits (of the GMBUS0 register). This table has HDMIB.
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