[PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes
djkurtz at chromium.org
Thu Mar 29 01:46:39 PDT 2012
On Thu, Mar 29, 2012 at 2:41 AM, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz <djkurtz at chromium.org> wrote:
>> The GMBUS controller GMBUS3 register is double-buffered. Take advantage
>> of this by writing two 4-byte words before the first wait for HW_RDY.
>> This helps keep the GMBUS controller from becoming idle during long writes.
>> Signed-off-by: Daniel Kurtz <djkurtz at chromium.org>
> "For byte counts that are greater than four bytes, this register will be
> written with subsequent data only after the HW_RDY status bit is set"
> Hmm, I had interpretted that as should only be. But if you take into
> account that the register is indeed double-buffered, it does make sense
> that the hardware itself is only updated after the HW_RDY signal.
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
In fact, during my experiments using the GMBUS interrupts, the HW_RDY
interrupt would only trigger for transactions > 4 bytes after 2 writes
> Chris Wilson, Intel Open Source Technology Centre
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