[PATCH 2/4] drm/radeon: convert fence to uint64_t
deathsimple at vodafone.de
Thu May 3 04:39:49 PDT 2012
On 03.05.2012 09:21, Michel Dänzer wrote:
> On Mit, 2012-05-02 at 16:20 -0400, j.glisse at gmail.com wrote:
>> From: Jerome Glisse<jglisse at redhat.com>
>> This convert fence to use uint64_t sequence number intention is
>> to use the fact that uin64_t is big enough that we don't need to
>> care about wrap around.
>> Tested with and without writeback using 0xFFFFF000 as initial
>> fence sequence and thus allowing to test the wrap around from
>> 32bits to 64bits.
>> Signed-off-by: Jerome Glisse<jglisse at redhat.com>
>> diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
>> index 7733429..6da1535 100644
>> --- a/drivers/gpu/drm/radeon/radeon_fence.c
>> +++ b/drivers/gpu/drm/radeon/radeon_fence.c
>> @@ -386,9 +388,9 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
>> rdev->fence_drv[ring].scratch_reg -
>> - rdev->fence_drv[ring].cpu_addr =rdev->wb.wb[index/4];
>> + rdev->fence_drv[ring].cpu_addr =u64*)&rdev->wb.wb[index/4];
> Might want to ensure cpu_addr is 64 bit aligned, or there might be
> trouble on some architectures.
> With this change, Cayman cards will already use six scratch registers
> for the rings. It won't be possible to extend this scheme for even one
> additional ring, will it?
That won't work anyway, since not all rings can deal with 64 bit fences,
so we need to still use 32 bit signaling and extend them to 64 bit while
processing the fence value.
Already working on that.
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