[PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer driver

[Inki Dae]

2012년 9월 13일 목요일에 Joonyoung Shim<jy0922.shim at samsung.com>님이 작성:
> On 09/13/2012 11:53 AM, Inki Dae wrote:
>
> -----Original Message-----
> From: Joonyoung Shim [mailto:jy0922.shim at samsung.com]
> Sent: Thursday, September 13, 2012 10:44 AM
> To: Rahul Sharma
> Cc: dri-devel at lists.freedesktop.org; sw0312.kim at samsung.com;
> inki.dae at samsung.com; kyungmin.park at samsung.com; prashanth.g at samsung.com;
> joshi at samsung.com; s.shirish at samsung.com; fahad.k at samsung.com;
> l.krishna at samsung.com; r.sh.open at gmail.com
> Subject: Re: [PATCH 1/3] drm: exynos: hdmi: add exynos5 support to mixer
> driver
>
> Hi, Rahul.
>
> On 09/12/2012 09:08 PM, Rahul Sharma wrote:
>
> Added support for exynos5 to drm mixer driver. Exynos5 works
> with dt enabled while in exynos4 mixer device information can
> be passed either way (dt or plf data). This situation is taken
> cared.
>
> Signed-off-by: Rahul Sharma <rahul.sharma at samsung.com>
> Signed-off-by: Shirish S <s.shirish at samsung.com>
> Signed-off-by: Fahad Kunnathadi <fahad.k at samsung.com>
> ---
>    drivers/gpu/drm/exynos/exynos_mixer.c |  153
>
> ++++++++++++++++++++++++++++++---
>
>    drivers/gpu/drm/exynos/regs-mixer.h   |    2 +
>    2 files changed, 142 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>
> b/drivers/gpu/drm/exynos/exynos_mixer.c
>
> index 8a43ee1..7d04a40 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -71,6 +71,7 @@ struct mixer_resources {
>         struct clk              *sclk_mixer;
>         struct clk              *sclk_hdmi;
>         struct clk              *sclk_dac;
> +       bool                    is_soc_exynos5;
>    };
>
>    struct mixer_context {
> @@ -251,7 +252,8 @@ static void mixer_vsync_set_update(struct
>
> mixer_context *ctx, bool enable)
>
>         mixer_reg_writemask(res, MXR_STATUS, enable ?
>                         MXR_STATUS_SYNC_ENABLE : 0,
MXR_STATUS_SYNC_ENABLE);
>
> -       vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
> +       if (!res->is_soc_exynos5)
> +               vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
>                         VP_SHADOW_UPDATE_ENABLE : 0);
>    }
>
> @@ -615,15 +617,21 @@ static void mixer_win_reset(struct mixer_context
>
> *ctx)
>
>         val = MXR_GRP_CFG_ALPHA_VAL(0);
>         mixer_reg_write(res, MXR_VIDEO_CFG, val);
>
> -       /* configuration of Video Processor Registers */
> -       vp_win_reset(ctx);
> -       vp_default_filter(res);
> +       if (!res->is_soc_exynos5) {
> +               /* configuration of Video Processor Registers */
> +               vp_win_reset(ctx);
> +               vp_default_filter(res);
> +       }
>
>         /* disable all layers */
>         mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
>         mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
>         mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
>
> +       /* enable vsync interrupt after mixer reset*/
> +       mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
> +                       MXR_INT_EN_VSYNC);
> +
>         mixer_vsync_set_update(ctx, true);
>         spin_unlock_irqrestore(&res->reg_slock, flags);
>    }
> @@ -645,7 +653,8 @@ static void mixer_poweron(struct mixer_context *ctx)
>         pm_runtime_get_sync(ctx->dev);
>
>         clk_enable(res->mixer);
> -       clk_enable(res->vp);
> +       if (!res->is_soc_exynos5)
> +               clk_enable(res->vp);
>         clk_enable(res->sclk_mixer);
>
>         mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
> @@ -666,7 +675,8 @@ static void mixer_poweroff(struct mixer_context
>
> *ctx)
>
>         ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
>
>         clk_disable(res->mixer
>
> Let's think to disassociate hdmi and mixer. I have plan to unify to one
> many things of exynos hdmi. Above problem occurs because exynos5 doesn't
> have video processor ip. Even if we use a field such is_soc_exynos5, the
> is_soc_exynos5 is unsuitable naming if other exynos SoC also doesn't
> have video processor ip.
>

one more thing, exynos5 uses GScaler instead of Video processor. the
GScaler can be also used as post processor but exynos5 spec has no any
descriptions to this. so we should check that first and next let's update
things related to hdmi.
_______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20120913/08ba9418/attachment.html>