[Intel-gfx] [PATCH 7/8] drm/i915: Added debugfs support for PSR Status
Paulo Zanoni
przanoni at gmail.com
Thu Feb 28 09:44:06 PST 2013
Hi
2013/2/25 Rodrigo Vivi <rodrigo.vivi at gmail.com>:
> Adding support for PSR Status, PSR entry counter and performance counters.
> Heavily based on initial work from Shobhit.
>
> Credits-by: Shobhit Kumar <shobhit.kumar at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 92 +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 24 ++++++++++
> 2 files changed, 116 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7c65ab8..01021f6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1680,6 +1680,97 @@ static int i915_dpio_info(struct seq_file *m, void *data)
> return 0;
> }
>
> +
> +static int i915_edp_psr_status(struct seq_file *m, void *data)
> +{
> + struct drm_info_node *node = m->private;
> + struct drm_device *dev = node->minor->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned int count;
> + u32 psrctl, psrstat, psrperf;
> +
> + psrctl = I915_READ(EDP_PSR_CTL);
> + seq_printf(m, "PSR Enabled: %s\n",
> + yesno(psrctl & EDP_PSR_ENABLE));
> +
> + psrstat = I915_READ(EDP_PSR_STATUS_CTL);
> +
> + seq_printf(m, "PSR Current State: ");
> + switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
> + case EDP_PSR_STATUS_STATE_IDLE:
> + seq_printf(m, "Reset state\n");
> + break;
> + case EDP_PSR_STATUS_STATE_SRDONACK:
> + seq_printf(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
> + break;
> + case EDP_PSR_STATUS_STATE_SRDENT:
> + seq_printf(m, "SRD entry\n");
> + break;
> + case EDP_PSR_STATUS_STATE_BUFOFF:
> + seq_printf(m, "Wait for buffer turn off\n");
> + break;
> + case EDP_PSR_STATUS_STATE_BUFON:
> + seq_printf(m, "Wait for buffer turn on\n");
> + break;
> + case EDP_PSR_STATUS_STATE_AUXACK:
> + seq_printf(m, "Wait for AUX to acknowledge on SRD exit\n");
> + break;
> + case EDP_PSR_STATUS_STATE_SRDOFFACK:
> + seq_printf(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
> + break;
> + default:
> + seq_printf(m, "Unknown\n");
> + break;
> + }
> +
> + seq_printf(m, "Link Status: ");
> + switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
> + case EDP_PSR_STATUS_LINK_FULL_OFF:
> + seq_printf(m, "Link is fully off\n");
> + break;
> + case EDP_PSR_STATUS_LINK_FULL_ON:
> + seq_printf(m, "Link is fully on\n");
> + break;
> + case EDP_PSR_STATUS_LINK_STANDBY:
> + seq_printf(m, "Link is in standby\n");
> + break;
> + default:
> + seq_printf(m, "Unknown\n");
> + break;
> + }
> +
> + seq_printf(m, "PSR Entry Count: %u\n",
> + psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
> + EDP_PSR_STATUS_COUNT_MASK);
> +
> + seq_printf(m, "Max Sleep Timer Counter: %u\n",
> + psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
> + EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
> +
> + seq_printf(m, "Had AUX error: %s\n",
> + yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
> +
> + seq_printf(m, "Sending AUX: %s\n",
> + yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
> +
> + seq_printf(m, "Sending Idle: %s\n",
> + yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
> +
> + seq_printf(m, "Sending TP2 TP3: %s\n",
> + yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
> +
> + seq_printf(m, "Sending TP1: %s\n",
> + yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
> +
> + seq_printf(m, "Idle Count: %u\n",
> + psrstat & EDP_PSR_STATUS_IDLE_MASK);
> +
> + psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
> + seq_printf(m, "Performance Counter: %u\n", psrperf);
> +
> + return 0;
> +}
> +
> static ssize_t
> i915_wedged_read(struct file *filp,
> char __user *ubuf,
> @@ -2249,6 +2340,7 @@ static struct drm_info_list i915_debugfs_list[] = {
> {"i915_swizzle_info", i915_swizzle_info, 0},
> {"i915_ppgtt_info", i915_ppgtt_info, 0},
> {"i915_dpio", i915_dpio_info, 0},
> + {"i915_edp_psr_status", i915_edp_psr_status, 0},
> };
> #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1e31f23..1f7e666 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1615,6 +1615,30 @@
>
> #define EDP_PSR_STATUS_CTL 0x64840
> #define EDP_PSR_STATUS_STATE_MASK (7<<29)
> +#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
> +#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
> +#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
> +#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
> +#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
> +#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
> +#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
> +#define EDP_PSR_STATUS_LINK_MASK (3<<29)
> +#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<29)
> +#define EDP_PSR_STATUS_LINK_FULL_ON (1<<29)
> +#define EDP_PSR_STATUS_LINK_STANDBY (2<<29)
The 4 lines above are wrong. It's (x<<26).
> +#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
> +#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
> +#define EDP_PSR_STATUS_COUNT_SHIFT 16
> +#define EDP_PSR_STATUS_COUNT_MASK 0xf
> +#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
> +#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
> +#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
> +#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
> +#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
> +#define EDP_PSR_STATUS_IDLE_MASK 0xf
> +
> +#define EDP_PSR_PERF_CNT 0x64844
> +#define EDP_PSR_PERF_CNT_MASK 0xffffff
>
> #define EDP_PSR_DEBUG_CTL 0x64860
> #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
> --
> 1.8.1.2
>
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--
Paulo Zanoni
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