[PATCH] radeon: Fix surface register on r100

[Mark Kettenis]

> Date: Fri, 5 Jul 2013 10:11:18 -0400
> From: Alex Deucher <alexdeucher at gmail.com>
> 
> On Wed, Jul 3, 2013 at 6:40 PM, Mark Kettenis <mark.kettenis at xs4all.nl> wrote:
> > Working on KMS support on OpenBSD/sparc64, I ended up with the initial
> > framebuffer on a Sun XVR-100 card (Radeon 7000/VE, RV100 with
> > OpenFirmware) being tiled when none of the tiling flags were set.
> > Tracked it down to an issue with r100_set_surface_reg().  The tiling
> > bits on these older chips are a bit different than the later ones.
> > There is no real flag for macro tiled buffer;
> > RADEON_SURF_TILE_COLOR_MACRO is 0.  So if we aren't actually tiling,
> > we can't actually indicate that by not setting that bit.  Instead we
> > should make sure that we set the size of tiles to 0.  The diff below
> > reorganizes the code handling these variants a bit to do that.  It
> > also seems that you can't have a buffer that's only micro tiled.  The
> > diff turns that into a BUG(), but perhaps that isn't such a good idea
> > since I believe that userland can actually request such a tiling and
> > the ioctl code doesn't check this.  So perhaps it should just fall
> > through into the no-tiling case.
> 
> It's a little bit funny on r1xx compared to newer asics:
> 
>                       SURFACE0_INFO - RW - 32 bits - [MMReg:0xB0C]
>            Field Name        Bits    Default
>  Description
> SURF0_PITCHSEL                9:0      0x0    Pitch in octawords (16
> bytes) of Surface 0. A value of 0
>                                               disables tiling in Surface 0.
> SURF0_TILE_MODE 17:16  0x0    Mode of tiling for Surface 0. Set
> SURF0_PITCHSEL to 0 to
>                               disable tiling surface 0.
>                                 0=Disable MicroTiling
>                                 1=Enable MicroTiling
>                                 2=32 bit Z tiling
>                                 3=16 bit Z tiling
> 
> Does the attached patch fix it?

Yes, that diff fixes it as well.

Thanks,

Mark