[patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800()

[Maarten Lankhorst]

Op 12-07-13 08:33, Dan Carpenter schreef:
> We care about the upper 32 bits here so we have to use 1ULL instead of 1
> to avoid a shift wrapping bug.
>
> Signed-off-by: Dan Carpenter <dan.carpenter at oracle.com>
>
> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> index 64dca26..fe67415 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> @@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
>  			} while (!tpcnr[gpc]);
>  			tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
>  
> -			tpc_set |= 1 << ((gpc * 8) + tpc);
> +			tpc_set |= 1ULL << ((gpc * 8) + tpc);
>  		}
>  
>  		nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
Reviewed-by: Maarten Lankhorst <maarten.lankhorst at canonical.com>

Any other code in nouveau that looks bugged?