[PATCH 6/8] drm/radeon: sun/hainan chips do not have UVD
Alex Deucher
alexdeucher at gmail.com
Tue May 14 07:56:34 PDT 2013
On Tue, May 14, 2013 at 3:55 AM, Christian König
<deathsimple at vodafone.de> wrote:
> Am 13.05.2013 22:55, schrieb alexdeucher at gmail.com:
>
>> From: Alex Deucher <alexander.deucher at amd.com>
>>
>> Skip UVD handling on them.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>
>
> That patch should be unnecessary, just let radeon_uvd_init return an error
> for hainan.
>
> We already handle it like this for RV770 and if the firmware isn't found
> (the later just generates a warning).
>
> The only thing I can see so far that isn't handled is writing to the
> UVD_UDEC_*_ADDR_CONFIG registers, but those shouldn't hurt us.
>
Unless you feel really strongly , I'd prefer to keep it as there are
future features we are working on that are also tied to UVD support.
Alex
> Christian.
>
>
>> ---
>> drivers/gpu/drm/radeon/radeon.h | 1 +
>> drivers/gpu/drm/radeon/si.c | 72
>> ++++++++++++++++++++++++---------------
>> 2 files changed, 45 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon.h
>> b/drivers/gpu/drm/radeon/radeon.h
>> index ec26d68..142ce6c 100644
>> --- a/drivers/gpu/drm/radeon/radeon.h
>> +++ b/drivers/gpu/drm/radeon/radeon.h
>> @@ -1694,6 +1694,7 @@ struct radeon_device {
>> int num_crtc; /* number of crtcs */
>> struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex
>> */
>> bool audio_enabled;
>> + bool has_uvd;
>> struct r600_audio audio_status; /* audio stuff */
>> struct notifier_block acpi_nb;
>> /* only one userspace can use Hyperz features or CMASK at a time
>> */
>> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
>> index 798b8b3..4b07820 100644
>> --- a/drivers/gpu/drm/radeon/si.c
>> +++ b/drivers/gpu/drm/radeon/si.c
>> @@ -2635,9 +2635,11 @@ static void si_gpu_init(struct radeon_device *rdev)
>> WREG32(HDP_ADDR_CONFIG, gb_addr_config);
>> WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
>> WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
>> - WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
>> - WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
>> - WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
>> + if (rdev->has_uvd) {
>> + WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
>> + WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
>> + WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
>> + }
>> si_tiling_mode_table_init(rdev);
>> @@ -5197,15 +5199,17 @@ static int si_startup(struct radeon_device
>> *rdev)
>> return r;
>> }
>> - r = rv770_uvd_resume(rdev);
>> - if (!r) {
>> - r = radeon_fence_driver_start_ring(rdev,
>> -
>> R600_RING_TYPE_UVD_INDEX);
>> + if (rdev->has_uvd) {
>> + r = rv770_uvd_resume(rdev);
>> + if (!r) {
>> + r = radeon_fence_driver_start_ring(rdev,
>> +
>> R600_RING_TYPE_UVD_INDEX);
>> + if (r)
>> + dev_err(rdev->dev, "UVD fences init error
>> (%d).\n", r);
>> + }
>> if (r)
>> - dev_err(rdev->dev, "UVD fences init error
>> (%d).\n", r);
>> + rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size =
>> 0;
>> }
>> - if (r)
>> - rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
>> /* Enable IRQ */
>> r = si_irq_init(rdev);
>> @@ -5264,16 +5268,18 @@ static int si_startup(struct radeon_device *rdev)
>> if (r)
>> return r;
>> - ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
>> - if (ring->ring_size) {
>> - r = radeon_ring_init(rdev, ring, ring->ring_size,
>> - R600_WB_UVD_RPTR_OFFSET,
>> - UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
>> - 0, 0xfffff, RADEON_CP_PACKET2);
>> - if (!r)
>> - r = r600_uvd_init(rdev);
>> - if (r)
>> - DRM_ERROR("radeon: failed initializing UVD
>> (%d).\n", r);
>> + if (rdev->has_uvd) {
>> + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
>> + if (ring->ring_size) {
>> + r = radeon_ring_init(rdev, ring, ring->ring_size,
>> + R600_WB_UVD_RPTR_OFFSET,
>> + UVD_RBC_RB_RPTR,
>> UVD_RBC_RB_WPTR,
>> + 0, 0xfffff,
>> RADEON_CP_PACKET2);
>> + if (!r)
>> + r = r600_uvd_init(rdev);
>> + if (r)
>> + DRM_ERROR("radeon: failed initializing UVD
>> (%d).\n", r);
>> + }
>> }
>> r = radeon_ib_pool_init(rdev);
>> @@ -5322,8 +5328,10 @@ int si_suspend(struct radeon_device *rdev)
>> radeon_vm_manager_fini(rdev);
>> si_cp_enable(rdev, false);
>> cayman_dma_stop(rdev);
>> - r600_uvd_rbc_stop(rdev);
>> - radeon_uvd_suspend(rdev);
>> + if (rdev->has_uvd) {
>> + r600_uvd_rbc_stop(rdev);
>> + radeon_uvd_suspend(rdev);
>> + }
>> si_irq_suspend(rdev);
>> radeon_wb_disable(rdev);
>> si_pcie_gart_disable(rdev);
>> @@ -5341,6 +5349,11 @@ int si_init(struct radeon_device *rdev)
>> struct radeon_ring *ring =
>> &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
>> int r;
>> + if (rdev->family == CHIP_HAINAN)
>> + rdev->has_uvd = false;
>> + else
>> + rdev->has_uvd = true;
>> +
>> /* Read BIOS */
>> if (!radeon_get_bios(rdev)) {
>> if (ASIC_IS_AVIVO(rdev))
>> @@ -5411,11 +5424,13 @@ int si_init(struct radeon_device *rdev)
>> ring->ring_obj = NULL;
>> r600_ring_init(rdev, ring, 64 * 1024);
>> - r = radeon_uvd_init(rdev);
>> - if (!r) {
>> - ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
>> - ring->ring_obj = NULL;
>> - r600_ring_init(rdev, ring, 4096);
>> + if (rdev->has_uvd) {
>> + r = radeon_uvd_init(rdev);
>> + if (!r) {
>> + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
>> + ring->ring_obj = NULL;
>> + r600_ring_init(rdev, ring, 4096);
>> + }
>> }
>> rdev->ih.ring_obj = NULL;
>> @@ -5463,7 +5478,8 @@ void si_fini(struct radeon_device *rdev)
>> radeon_vm_manager_fini(rdev);
>> radeon_ib_pool_fini(rdev);
>> radeon_irq_kms_fini(rdev);
>> - radeon_uvd_fini(rdev);
>> + if (rdev->has_uvd)
>> + radeon_uvd_fini(rdev);
>> si_pcie_gart_fini(rdev);
>> r600_vram_scratch_fini(rdev);
>> radeon_gem_fini(rdev);
>
>
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