[PATCH 2/2] drm/tegra: Obtain head number from DT

[Thierry Reding]

On Mon, Jan 13, 2014 at 10:46:45AM -0700, Stephen Warren wrote:
> On 01/13/2014 07:21 AM, Thierry Reding wrote:
> > The head number of a given display controller is fixed in hardware and
> > required to program outputs appropriately. Relying on the driver probe
> > order to determine this number will not work, since that could yield a
> > situation where the second head was probed first and would be assigned
> > head number 0 instead of 1.
> 
> This change makes the new properties mandatory, yet they aren't part of
> the DT files yet. So, won't this patch break all display on Tegra?

I don't think it'll make anything worse than it currently is, since both
display controllers can't run at the same time with the current code.

They can do so on Dalmore, so I guess that would be broken by the patch.

> To avoid having to modify the Tegra DTs in this patch, can't the code
> fall back to the existing broken algorithm if the property is missing, i.e.:
> 
> > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
> 
> > -	dc->pipe = tegra->drm->mode_config.num_crtc;
> 
> Instead,:
> 
> 	if (dc->pipe == -1)
> 		dc->pipe = tegra->drm->mode_config.num_crtc;
> 
> > +static int tegra_dc_parse_dt(struct tegra_dc *dc)
> > +{
> > +	u32 value;
> > +	int err;
> > +
> > +	err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
> > +	if (err < 0)
> > +		return err;
> > +
> > +	dc->pipe = value;
> 
> Instead:
> 
> 	err = ...
> 	if (!err)
> 		dc->pipe = value;
> 	else
> 		/* Perhaps also emit an error message here */
> 		dc->pipe = -1;

Yeah, that should work. It's still suboptimal because we fallback to
something that's broken and known not to work.

My original proposal was to make the dc->pipe assignment depend on the
physical address of the display controller's registers. That's ugly,
but all SoCs in existence do use the very same offset. So we could
reason that for anything that's still using the old DTB files we can
rely on the physical address of the registers, while any new DTBs
should include the new nvidia,head property.

I have a feeling that you won't like it, though.

One other method would be to iterate over all DT nodes that match the
display controller compatible and use the index for the pipe number.
That should fix the current issues, but is still a wee bit hackish
because it assumes that nodes in DTB will be in the same order as in
the DTS. That has been true since the beginning of DT on Linux AFAIK
and therefore should be reasonably safe.

Thierry
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: not available
URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140114/b20e2b37/attachment.pgp>