[PATCH] dt-bindings: display: bridge: lvds-codec: Fix spacing

[Marek Vasut]

Add missing spaces to make the diagrams readable, no functional change.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Cc: Rob Herring <robh+dt at kernel.org>
Cc: Sam Ravnborg <sam at ravnborg.org>
Cc: devicetree at vger.kernel.org
To: dri-devel at lists.freedesktop.org
---
 .../devicetree/bindings/display/panel/lvds.yaml      | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml
index 31164608ba1d..06d7ca692d0d 100644
--- a/Documentation/devicetree/bindings/display/panel/lvds.yaml
+++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml
@@ -52,9 +52,9 @@ properties:
         [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
 
       Slot	    0       1       2       3       4       5       6
-            ________________                         _________________
+                ________________                         _________________
       Clock	                \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
+                  ______  ______  ______  ______  ______  ______  ______
       DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
       DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
       DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
@@ -63,9 +63,9 @@ properties:
         specifications. Data are transferred as follows on 4 LVDS lanes.
 
       Slot	    0       1       2       3       4       5       6
-            ________________                         _________________
+                ________________                         _________________
       Clock	                \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
+                  ______  ______  ______  ______  ______  ______  ______
       DATA0	><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
       DATA1	><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
       DATA2	><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
@@ -75,9 +75,9 @@ properties:
         Data are transferred as follows on 4 LVDS lanes.
 
       Slot	    0       1       2       3       4       5       6
-            ________________                         _________________
+                ________________                         _________________
       Clock	                \_______________________/
-              ______  ______  ______  ______  ______  ______  ______
+                  ______  ______  ______  ______  ______  ______  ______
       DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
       DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
       DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
-- 
2.30.2