[PATCH 1/3] i915/gvt: seperate tracked MMIO table from handlers.c

kernel test robot lkp at intel.com
Thu Nov 11 23:32:37 UTC 2021


Hi Zhi,

I love your patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.15 next-20211111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/8d4393b277b5196206271d5191d25fe61b1b34f1
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Zhi-Wang/i915-gvt-seperate-tracked-MMIO-table-from-handlers-c/20211109-052907
        git checkout 8d4393b277b5196206271d5191d25fe61b1b34f1
        # save the attached .config to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All errors (new ones prefixed by >>):

   In file included from <command-line>:
   drivers/gpu/drm/i915/gvt/mmio_table.h:85:52: error: 'struct intel_gvt' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
      85 | static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
         |                                                    ^~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h: In function 'intel_gvt_init_generic_mmio_info':
>> drivers/gpu/drm/i915/gvt/mmio_table.h:87:41: error: dereferencing pointer to incomplete type 'struct intel_gvt'
      87 |  struct drm_i915_private *dev_priv = gvt->gt->i915;
         |                                         ^~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:8: error: implicit declaration of function 'new_mmio_info' [-Werror=implicit-function-declaration]
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |        ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
      62 |  MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
         |  ^~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:36:27: error: implicit declaration of function 'i915_mmio_reg_offset' [-Werror=implicit-function-declaration]
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                           ^~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:62:2: note: in expansion of macro 'MMIO_F'
      62 |  MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
         |  ^~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:16: error: implicit declaration of function 'RING_IMR' [-Werror=implicit-function-declaration]
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |                ^~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: error: 'RENDER_RING_BASE' undeclared (first use in this function)
      62 |  MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
         |                ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:62:16: note: each undeclared identifier is reported only once for each function it appears in
      62 |  MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
         |                ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:26: error: 'D_ALL' undeclared (first use in this function)
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |                          ^~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |                 ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:91:36: error: 'NULL' undeclared (first use in this function)
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |                                    ^~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:20: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |                    ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:1:1: note: 'NULL' is defined in header '<stddef.h>'; did you forget to '#include <stddef.h>'?
     +++ |+#include <stddef.h>
       1 | /*
>> drivers/gpu/drm/i915/gvt/mmio_table.h:92:3: error: 'intel_vgpu_reg_imr_handler' undeclared (first use in this function)
      92 |   intel_vgpu_reg_imr_handler);
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |                       ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:63:16: error: 'BLT_RING_BASE' undeclared (first use in this function)
      63 |  MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
         |                ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:64:16: error: 'GEN6_BSD_RING_BASE' undeclared (first use in this function)
      64 |  MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
         |                ^~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:65:16: error: 'VEBOX_RING_BASE' undeclared (first use in this function)
      65 |  MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
         |                ^~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:6: error: implicit declaration of function 'HAS_ENGINE' [-Werror=implicit-function-declaration]
      66 |  if (HAS_ENGINE(gvt->gt, VCS1)) \
         |      ^~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:66:26: error: 'VCS1' undeclared (first use in this function)
      66 |  if (HAS_ENGINE(gvt->gt, VCS1)) \
         |                          ^~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:67:17: error: 'GEN8_BSD2_RING_BASE' undeclared (first use in this function)
      67 |   MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
         |                 ^~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:91:2: note: in expansion of macro 'MMIO_RING_DFH'
      91 |  MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
         |  ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:94:11: error: 'SDEIMR' undeclared (first use in this function)
      94 |  MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
         |           ^~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:94:2: note: in expansion of macro 'MMIO_DFH'
      94 |  MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
         |  ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:11: error: 'SDEIER' undeclared (first use in this function)
      95 |  MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
         |           ^~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
      95 |  MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
         |  ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:95:35: error: 'intel_vgpu_reg_ier_handler' undeclared (first use in this function)
      95 |  MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
         |                                   ^~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |                       ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:95:2: note: in expansion of macro 'MMIO_DFH'
      95 |  MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
         |  ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:11: error: 'SDEIIR' undeclared (first use in this function)
      96 |  MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
         |           ^~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
      96 |  MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
         |  ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:96:35: error: 'intel_vgpu_reg_iir_handler' undeclared (first use in this function)
      96 |  MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
         |                                   ^~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |                       ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:96:2: note: in expansion of macro 'MMIO_DFH'
      96 |  MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
         |  ^~~~~~~~
>> drivers/gpu/drm/i915/gvt/mmio_table.h:97:9: error: 'SDEISR' undeclared (first use in this function)
      97 |  MMIO_D(SDEISR, D_ALL);
         |         ^~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:97:2: note: in expansion of macro 'MMIO_D'
      97 |  MMIO_D(SDEISR, D_ALL);
         |  ^~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:99:16: error: implicit declaration of function 'RING_HWSTAM' [-Werror=implicit-function-declaration]
      99 |  MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
         |                ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:74:2: note: in expansion of macro 'MMIO_RING_F'
      74 |  MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:99:2: note: in expansion of macro 'MMIO_RING_DFH'
      99 |  MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
         |  ^~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:102:10: error: 'GEN8_GAMW_ECO_DEV_RW_IA' undeclared (first use in this function)
     102 |  MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
         |          ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
     102 |  MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
         |  ^~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:102:35: error: 'D_BDW_PLUS' undeclared (first use in this function)
     102 |  MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
         |                                   ^~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:17: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |                 ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
     102 |  MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
         |  ^~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:103:3: error: 'gamw_echo_dev_rw_ia_write' undeclared (first use in this function)
     103 |   gamw_echo_dev_rw_ia_write);
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:23: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |                       ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:102:2: note: in expansion of macro 'MMIO_DH'
     102 |  MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
         |  ^~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:105:14: error: 'BSD_HWS_PGA_GEN7' undeclared (first use in this function)
     105 |  MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |              ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
     105 |  MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:56:17: error: 'F_GMADR' undeclared (first use in this function)
      56 |  MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
         |                 ^~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |   ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
     105 |  MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:56:27: error: 'F_CMD_ACCESS' undeclared (first use in this function)
      56 |  MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
         |                           ^~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:37:3: note: in definition of macro 'MMIO_F'
      37 |   f, s, am, rm, d, r, w); \
         |   ^
   drivers/gpu/drm/i915/gvt/mmio_table.h:105:2: note: in expansion of macro 'MMIO_GM_RDR'
     105 |  MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:106:14: error: 'BLT_HWS_PGA_GEN7' undeclared (first use in this function)
     106 |  MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |              ^~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:106:2: note: in expansion of macro 'MMIO_GM_RDR'
     106 |  MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:107:14: error: 'VEBOX_HWS_PGA_GEN7' undeclared (first use in this function)
     107 |  MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |              ^~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:107:2: note: in expansion of macro 'MMIO_GM_RDR'
     107 |  MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
         |  ^~~~~~~~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:109:24: error: implicit declaration of function '_MMIO' [-Werror=implicit-function-declaration]
     109 | #define RING_REG(base) _MMIO((base) + 0x28)
         |                        ^~~~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:36:48: note: in definition of macro 'MMIO_F'
      36 |  ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
         |                                                ^~~
   drivers/gpu/drm/i915/gvt/mmio_table.h:62:9: note: in expansion of macro 'RING_REG'
      62 |  MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \


vim +87 drivers/gpu/drm/i915/gvt/mmio_table.h

    27	
    28	#ifdef GENERATE_MMIO_TABLE_IN_I915
    29	#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
    30		ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg)); \
    31		if (ret) \
    32			return ret; \
    33	} while (0)
    34	#else
    35	#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
  > 36		ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
    37			f, s, am, rm, d, r, w); \
    38		if (ret) \
    39			return ret; \
    40	} while (0)
    41	#endif
    42	
    43	#define MMIO_D(reg, d) \
    44		MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
    45	
    46	#define MMIO_DH(reg, d, r, w) \
    47		MMIO_F(reg, 4, 0, 0, 0, d, r, w)
    48	
    49	#define MMIO_DFH(reg, d, f, r, w) \
    50		MMIO_F(reg, 4, f, 0, 0, d, r, w)
    51	
    52	#define MMIO_GM(reg, d, r, w) \
    53		MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
    54	
    55	#define MMIO_GM_RDR(reg, d, r, w) \
  > 56		MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
    57	
    58	#define MMIO_RO(reg, d, f, rm, r, w) \
  > 59		MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
    60	
    61	#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
  > 62		MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
  > 63		MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
  > 64		MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
  > 65		MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
  > 66		if (HAS_ENGINE(gvt->gt, VCS1)) \
  > 67			MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
    68	} while (0)
    69	
    70	#define MMIO_RING_D(prefix, d) \
    71		MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
    72	
    73	#define MMIO_RING_DFH(prefix, d, f, r, w) \
    74		MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
    75	
    76	#define MMIO_RING_GM(prefix, d, r, w) \
    77		MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
    78	
    79	#define MMIO_RING_GM_RDR(prefix, d, r, w) \
    80		MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
    81	
    82	#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
    83		MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
    84	
    85	static int intel_gvt_init_generic_mmio_info(struct intel_gvt *gvt)
    86	{
  > 87		struct drm_i915_private *dev_priv = gvt->gt->i915;
    88	
    89		int ret;
    90	
  > 91		MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
  > 92			intel_vgpu_reg_imr_handler);
    93	
  > 94		MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
  > 95		MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
  > 96		MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
  > 97		MMIO_D(SDEISR, D_ALL);
    98	
  > 99		MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
   100	
   101	
 > 102		MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
 > 103			gamw_echo_dev_rw_ia_write);
   104	
 > 105		MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
 > 106		MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
 > 107		MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
   108	
 > 109	#define RING_REG(base) _MMIO((base) + 0x28)
   110		MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
   111	#undef RING_REG
   112	
   113	#define RING_REG(base) _MMIO((base) + 0x134)
   114		MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
   115	#undef RING_REG
   116	
   117	#define RING_REG(base) _MMIO((base) + 0x6c)
 > 118		MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
   119	#undef RING_REG
 > 120		MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
   121	
   122		MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
 > 123		MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
   124		MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
 > 125		MMIO_D(GEN7_CXT_SIZE, D_ALL);
   126	
 > 127		MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
 > 128		MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
 > 129		MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
 > 130		MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
 > 131		MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
   132	
   133		/* RING MODE */
   134	#define RING_REG(base) _MMIO((base) + 0x29c)
   135		MMIO_RING_DFH(RING_REG, D_ALL,
 > 136			F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
 > 137			ring_mode_mmio_write);
   138	#undef RING_REG
   139	
 > 140		MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
   141			NULL, NULL);
 > 142		MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
   143				NULL, NULL);
 > 144		MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
   145				mmio_read_from_hw, NULL);
 > 146		MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
   147				mmio_read_from_hw, NULL);
   148	
 > 149		MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 > 150		MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
   151			NULL, NULL);
 > 152		MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 > 153		MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
   154		MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
   155	
   156		MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 > 157		MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
   158		MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 > 159		MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
   160			 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
   161		MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 > 162		MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
 > 163		MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
   164			NULL, NULL);
 > 165		MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
   166			 NULL, NULL);
   167		MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
   168		MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
   169		MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
   170		MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
   171		MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
   172		MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
   173		MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
   174		MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 > 175		MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 > 176		MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
   177	
   178		/* display */
   179		MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
   180		MMIO_D(_MMIO(0x602a0), D_ALL);
   181	
   182		MMIO_D(_MMIO(0x65050), D_ALL);
   183		MMIO_D(_MMIO(0x650b4), D_ALL);
   184	
   185		MMIO_D(_MMIO(0xc4040), D_ALL);
 > 186		MMIO_D(DERRMR, D_ALL);
   187	
 > 188		MMIO_D(PIPEDSL(PIPE_A), D_ALL);
 > 189		MMIO_D(PIPEDSL(PIPE_B), D_ALL);
 > 190		MMIO_D(PIPEDSL(PIPE_C), D_ALL);
 > 191		MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
   192	
 > 193		MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
   194		MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
   195		MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
   196		MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
   197	
 > 198		MMIO_D(PIPESTAT(PIPE_A), D_ALL);
   199		MMIO_D(PIPESTAT(PIPE_B), D_ALL);
   200		MMIO_D(PIPESTAT(PIPE_C), D_ALL);
   201		MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
   202	
 > 203		MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
   204		MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
   205		MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
   206		MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
   207	
 > 208		MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
   209		MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
   210		MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
   211		MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
   212	
 > 213		MMIO_D(CURCNTR(PIPE_A), D_ALL);
   214		MMIO_D(CURCNTR(PIPE_B), D_ALL);
   215		MMIO_D(CURCNTR(PIPE_C), D_ALL);
   216	
 > 217		MMIO_D(CURPOS(PIPE_A), D_ALL);
   218		MMIO_D(CURPOS(PIPE_B), D_ALL);
   219		MMIO_D(CURPOS(PIPE_C), D_ALL);
   220	
 > 221		MMIO_D(CURBASE(PIPE_A), D_ALL);
   222		MMIO_D(CURBASE(PIPE_B), D_ALL);
   223		MMIO_D(CURBASE(PIPE_C), D_ALL);
   224	
 > 225		MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
   226		MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
   227		MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
   228	
   229		MMIO_D(_MMIO(0x700ac), D_ALL);
   230		MMIO_D(_MMIO(0x710ac), D_ALL);
   231		MMIO_D(_MMIO(0x720ac), D_ALL);
   232	
   233		MMIO_D(_MMIO(0x70090), D_ALL);
   234		MMIO_D(_MMIO(0x70094), D_ALL);
   235		MMIO_D(_MMIO(0x70098), D_ALL);
   236		MMIO_D(_MMIO(0x7009c), D_ALL);
   237	
 > 238		MMIO_D(DSPCNTR(PIPE_A), D_ALL);
 > 239		MMIO_D(DSPADDR(PIPE_A), D_ALL);
 > 240		MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
 > 241		MMIO_D(DSPPOS(PIPE_A), D_ALL);
 > 242		MMIO_D(DSPSIZE(PIPE_A), D_ALL);
 > 243		MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
 > 244		MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
 > 245		MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
 > 246		MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
 > 247			reg50080_mmio_write);
   248	
   249		MMIO_D(DSPCNTR(PIPE_B), D_ALL);
   250		MMIO_D(DSPADDR(PIPE_B), D_ALL);
   251		MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
   252		MMIO_D(DSPPOS(PIPE_B), D_ALL);
   253		MMIO_D(DSPSIZE(PIPE_B), D_ALL);
   254		MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
   255		MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
   256		MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
   257		MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
   258			reg50080_mmio_write);
   259	
   260		MMIO_D(DSPCNTR(PIPE_C), D_ALL);
   261		MMIO_D(DSPADDR(PIPE_C), D_ALL);
   262		MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
   263		MMIO_D(DSPPOS(PIPE_C), D_ALL);
   264		MMIO_D(DSPSIZE(PIPE_C), D_ALL);
   265		MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
   266		MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
   267		MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
   268		MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
   269			reg50080_mmio_write);
   270	
 > 271		MMIO_D(SPRCTL(PIPE_A), D_ALL);
 > 272		MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
 > 273		MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
 > 274		MMIO_D(SPRPOS(PIPE_A), D_ALL);
 > 275		MMIO_D(SPRSIZE(PIPE_A), D_ALL);
 > 276		MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
 > 277		MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
 > 278		MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
 > 279		MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
 > 280		MMIO_D(SPROFFSET(PIPE_A), D_ALL);
 > 281		MMIO_D(SPRSCALE(PIPE_A), D_ALL);
 > 282		MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
 > 283		MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
   284			reg50080_mmio_write);
   285	
   286		MMIO_D(SPRCTL(PIPE_B), D_ALL);
   287		MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
   288		MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
   289		MMIO_D(SPRPOS(PIPE_B), D_ALL);
   290		MMIO_D(SPRSIZE(PIPE_B), D_ALL);
   291		MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
   292		MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
   293		MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
   294		MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
   295		MMIO_D(SPROFFSET(PIPE_B), D_ALL);
   296		MMIO_D(SPRSCALE(PIPE_B), D_ALL);
   297		MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
   298		MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
   299			reg50080_mmio_write);
   300	
   301		MMIO_D(SPRCTL(PIPE_C), D_ALL);
   302		MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
   303		MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
   304		MMIO_D(SPRPOS(PIPE_C), D_ALL);
   305		MMIO_D(SPRSIZE(PIPE_C), D_ALL);
   306		MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
   307		MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
   308		MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
   309		MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
   310		MMIO_D(SPROFFSET(PIPE_C), D_ALL);
   311		MMIO_D(SPRSCALE(PIPE_C), D_ALL);
   312		MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
   313		MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
   314			reg50080_mmio_write);
   315	
   316		MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
   317		MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
   318		MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
   319		MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
   320		MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
   321		MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
   322		MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
   323		MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
   324		MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
   325	
   326		MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
   327		MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
   328		MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
   329		MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
   330		MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
   331		MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
   332		MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
   333		MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
   334		MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
   335	
   336		MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
   337		MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
   338		MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
   339		MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
   340		MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
   341		MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
   342		MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
   343		MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
   344		MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
   345	
   346		MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
   347		MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
   348		MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
   349		MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
   350		MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
   351		MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
   352		MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
   353		MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
   354	
   355		MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
   356		MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
   357		MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
   358		MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
   359		MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
   360		MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
   361		MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
   362		MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
   363	
   364		MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
   365		MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
   366		MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
   367		MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
   368		MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
   369		MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
   370		MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
   371		MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
   372	
   373		MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
   374		MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
   375		MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
   376		MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
   377		MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
   378		MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
   379		MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
   380		MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
   381	
   382		MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
   383		MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
   384		MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
   385		MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
   386		MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
   387		MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
   388		MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
   389		MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
   390	
   391		MMIO_D(PF_CTL(PIPE_A), D_ALL);
   392		MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
   393		MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
   394		MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
   395		MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
   396	
   397		MMIO_D(PF_CTL(PIPE_B), D_ALL);
   398		MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
   399		MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
   400		MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
   401		MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
   402	
   403		MMIO_D(PF_CTL(PIPE_C), D_ALL);
   404		MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
   405		MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
   406		MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
   407		MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
   408	
   409		MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
   410		MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
   411		MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
   412		MMIO_D(WM1_LP_ILK, D_ALL);
   413		MMIO_D(WM2_LP_ILK, D_ALL);
   414		MMIO_D(WM3_LP_ILK, D_ALL);
   415		MMIO_D(WM1S_LP_ILK, D_ALL);
   416		MMIO_D(WM2S_LP_IVB, D_ALL);
   417		MMIO_D(WM3S_LP_IVB, D_ALL);
   418	
   419		MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
   420		MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
   421		MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
   422		MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
   423	
   424		MMIO_D(_MMIO(0x48268), D_ALL);
   425	
   426		MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
   427			gmbus_mmio_write);
   428		MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
   429		MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
   430	
   431		MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
   432			dp_aux_ch_ctl_mmio_write);
   433		MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
   434			dp_aux_ch_ctl_mmio_write);
   435		MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
   436			dp_aux_ch_ctl_mmio_write);
   437	
   438		MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
   439	
   440		MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
   441		MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
   442	
   443		MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
   444		MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
   445		MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
   446		MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
   447		MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
   448		MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
   449		MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
   450		MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
   451		MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
   452	
   453		MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
   454		MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
   455		MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
   456		MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
   457		MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
   458		MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
   459		MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
   460	
   461		MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
   462		MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
   463		MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
   464		MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
   465		MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
   466		MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
   467		MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
   468	
   469		MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
   470		MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
   471		MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
   472		MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
   473		MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
   474		MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
   475		MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
   476		MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
   477	
   478		MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
   479		MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
   480		MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
   481	
   482		MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
   483		MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
   484		MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
   485	
   486		MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
   487		MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
   488		MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
   489	
   490		MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
   491		MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
   492		MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
   493	
   494		MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
   495		MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
   496		MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
   497		MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
   498		MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
   499		MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
   500	
   501		MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
   502		MMIO_D(PCH_PP_DIVISOR, D_ALL);
   503		MMIO_D(PCH_PP_STATUS,  D_ALL);
   504		MMIO_D(PCH_LVDS, D_ALL);
   505		MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
   506		MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
   507		MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
   508		MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
   509		MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
   510		MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
   511		MMIO_D(PCH_DREF_CONTROL, D_ALL);
   512		MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
   513		MMIO_D(PCH_DPLL_SEL, D_ALL);
   514	
   515		MMIO_D(_MMIO(0x61208), D_ALL);
   516		MMIO_D(_MMIO(0x6120c), D_ALL);
   517		MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
   518		MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
   519	
   520		MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
   521		MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
   522		MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
   523		MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
   524		MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
   525		MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
   526	
   527		MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
   528			PORTA_HOTPLUG_STATUS_MASK
   529			| PORTB_HOTPLUG_STATUS_MASK
   530			| PORTC_HOTPLUG_STATUS_MASK
   531			| PORTD_HOTPLUG_STATUS_MASK,
   532			NULL, NULL);
   533	
   534		MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
   535		MMIO_D(FUSE_STRAP, D_ALL);
   536		MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
   537	
   538		MMIO_D(DISP_ARB_CTL, D_ALL);
   539		MMIO_D(DISP_ARB_CTL2, D_ALL);
   540	
   541		MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
   542		MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
   543		MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
   544	
   545		MMIO_D(SOUTH_CHICKEN1, D_ALL);
   546		MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
   547		MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
   548		MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
   549		MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
   550		MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
   551		MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
   552	
   553		MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
   554		MMIO_D(ILK_DPFC_CONTROL, D_ALL);
   555		MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
   556		MMIO_D(ILK_DPFC_STATUS, D_ALL);
   557		MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
   558		MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
   559		MMIO_D(ILK_FBC_RT_BASE, D_ALL);
   560	
   561		MMIO_D(IPS_CTL, D_ALL);
   562	
   563		MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
   564		MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
   565		MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
   566		MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
   567		MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
   568		MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
   569		MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
   570		MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
   571		MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
   572		MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
   573		MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
   574		MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
   575		MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
   576	
   577		MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
   578		MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
   579		MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
   580		MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
   581		MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
   582		MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
   583		MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
   584		MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
   585		MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
   586		MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
   587		MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
   588		MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
   589		MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
   590	
   591		MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
   592		MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
   593		MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
   594		MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
   595		MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
   596		MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
   597		MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
   598		MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
   599		MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
   600		MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
   601		MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
   602		MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
   603		MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
   604	
   605		MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
   606		MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
   607		MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
   608	
   609		MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
   610		MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
   611		MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
   612	
   613		MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
   614		MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
   615		MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
   616	
   617		MMIO_D(_MMIO(0x60110), D_ALL);
   618		MMIO_D(_MMIO(0x61110), D_ALL);
   619		MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
   620		MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
   621		MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
   622		MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
   623		MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
   624		MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
   625		MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
   626		MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
   627		MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
   628	
   629		MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
   630		MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
   631		MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
   632		MMIO_D(SPLL_CTL, D_ALL);
   633		MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
   634		MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
   635		MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
   636		MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
   637		MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
   638		MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
   639		MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
   640		MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
   641		MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
   642		MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
   643	
   644		MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
   645		MMIO_D(_MMIO(0x46508), D_ALL);
   646	
   647		MMIO_D(_MMIO(0x49080), D_ALL);
   648		MMIO_D(_MMIO(0x49180), D_ALL);
   649		MMIO_D(_MMIO(0x49280), D_ALL);
   650	
   651		MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
   652		MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
   653		MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
   654	
   655		MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
   656		MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
   657		MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
   658	
   659		MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
   660		MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
   661		MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
   662	
   663		MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
   664		MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
   665		MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
   666	
   667		MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
   668		MMIO_D(SBI_ADDR, D_ALL);
   669		MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
   670		MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
   671		MMIO_D(PIXCLK_GATE, D_ALL);
   672	
   673		MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
   674			dp_aux_ch_ctl_mmio_write);
   675	
   676		MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
   677		MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
   678		MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
   679		MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
   680		MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
   681	
   682		MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
   683		MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
   684		MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
   685		MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
   686		MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
   687	
   688		MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
   689		MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
   690		MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
   691		MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
   692		MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
   693	
   694		MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
   695		MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
   696		MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
   697		MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
   698		MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
   699	
   700		MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
   701		MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
   702		MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
   703	
   704		MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
   705		MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
   706		MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
   707		MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
   708	
   709		MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
   710		MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
   711		MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
   712		MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
   713	
   714		MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
   715		MMIO_D(FORCEWAKE_ACK, D_ALL);
   716		MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
   717		MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
   718		MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
   719		MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
   720		MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
   721		MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
   722		MMIO_D(ECOBUS, D_ALL);
   723		MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
   724		MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
   725		MMIO_D(GEN6_RPNSWREQ, D_ALL);
   726		MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
   727		MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
   728		MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
   729		MMIO_D(GEN6_RPSTAT1, D_ALL);
   730		MMIO_D(GEN6_RP_CONTROL, D_ALL);
   731		MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
   732		MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
   733		MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
   734		MMIO_D(GEN6_RP_CUR_UP, D_ALL);
   735		MMIO_D(GEN6_RP_PREV_UP, D_ALL);
   736		MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
   737		MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
   738		MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
   739		MMIO_D(GEN6_RP_UP_EI, D_ALL);
   740		MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
   741		MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
   742		MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
   743		MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
   744		MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
   745		MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
   746		MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
   747		MMIO_D(GEN6_RC_SLEEP, D_ALL);
   748		MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
   749		MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
   750		MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
   751		MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
   752		MMIO_D(GEN6_PMINTRMSK, D_ALL);
   753		MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
   754		MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
   755		MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
   756		MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
   757		MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
   758		MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
   759	
   760		MMIO_D(RSTDBYCTL, D_ALL);
   761	
   762		MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
   763		MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
   764		MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
   765	
   766		MMIO_D(TILECTL, D_ALL);
   767	
   768		MMIO_D(GEN6_UCGCTL1, D_ALL);
   769		MMIO_D(GEN6_UCGCTL2, D_ALL);
   770	
   771		MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
   772	
   773		MMIO_D(GEN6_PCODE_DATA, D_ALL);
   774		MMIO_D(_MMIO(0x13812c), D_ALL);
   775		MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
   776		MMIO_D(HSW_EDRAM_CAP, D_ALL);
   777		MMIO_D(HSW_IDICR, D_ALL);
   778		MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
   779	
   780		MMIO_D(_MMIO(0x3c), D_ALL);
   781		MMIO_D(_MMIO(0x860), D_ALL);
   782		MMIO_D(ECOSKPD, D_ALL);
   783		MMIO_D(_MMIO(0x121d0), D_ALL);
   784		MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
   785		MMIO_D(_MMIO(0x41d0), D_ALL);
   786		MMIO_D(GAC_ECO_BITS, D_ALL);
   787		MMIO_D(_MMIO(0x6200), D_ALL);
   788		MMIO_D(_MMIO(0x6204), D_ALL);
   789		MMIO_D(_MMIO(0x6208), D_ALL);
   790		MMIO_D(_MMIO(0x7118), D_ALL);
   791		MMIO_D(_MMIO(0x7180), D_ALL);
   792		MMIO_D(_MMIO(0x7408), D_ALL);
   793		MMIO_D(_MMIO(0x7c00), D_ALL);
   794		MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
   795		MMIO_D(_MMIO(0x911c), D_ALL);
   796		MMIO_D(_MMIO(0x9120), D_ALL);
   797		MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
   798	
   799		MMIO_D(GAB_CTL, D_ALL);
   800		MMIO_D(_MMIO(0x48800), D_ALL);
   801		MMIO_D(_MMIO(0xce044), D_ALL);
   802		MMIO_D(_MMIO(0xe6500), D_ALL);
   803		MMIO_D(_MMIO(0xe6504), D_ALL);
   804		MMIO_D(_MMIO(0xe6600), D_ALL);
   805		MMIO_D(_MMIO(0xe6604), D_ALL);
   806		MMIO_D(_MMIO(0xe6700), D_ALL);
   807		MMIO_D(_MMIO(0xe6704), D_ALL);
   808		MMIO_D(_MMIO(0xe6800), D_ALL);
   809		MMIO_D(_MMIO(0xe6804), D_ALL);
   810		MMIO_D(PCH_GMBUS4, D_ALL);
   811		MMIO_D(PCH_GMBUS5, D_ALL);
   812	
   813		MMIO_D(_MMIO(0x902c), D_ALL);
   814		MMIO_D(_MMIO(0xec008), D_ALL);
   815		MMIO_D(_MMIO(0xec00c), D_ALL);
   816		MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
   817		MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
   818		MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
   819		MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
   820		MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
   821		MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
   822		MMIO_D(_MMIO(0xec408), D_ALL);
   823		MMIO_D(_MMIO(0xec40c), D_ALL);
   824		MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
   825		MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
   826		MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
   827		MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
   828		MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
   829		MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
   830		MMIO_D(_MMIO(0xfc810), D_ALL);
   831		MMIO_D(_MMIO(0xfc81c), D_ALL);
   832		MMIO_D(_MMIO(0xfc828), D_ALL);
   833		MMIO_D(_MMIO(0xfc834), D_ALL);
   834		MMIO_D(_MMIO(0xfcc00), D_ALL);
   835		MMIO_D(_MMIO(0xfcc0c), D_ALL);
   836		MMIO_D(_MMIO(0xfcc18), D_ALL);
   837		MMIO_D(_MMIO(0xfcc24), D_ALL);
   838		MMIO_D(_MMIO(0xfd000), D_ALL);
   839		MMIO_D(_MMIO(0xfd00c), D_ALL);
   840		MMIO_D(_MMIO(0xfd018), D_ALL);
   841		MMIO_D(_MMIO(0xfd024), D_ALL);
   842		MMIO_D(_MMIO(0xfd034), D_ALL);
   843	
   844		MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
   845		MMIO_D(_MMIO(0x2054), D_ALL);
   846		MMIO_D(_MMIO(0x12054), D_ALL);
   847		MMIO_D(_MMIO(0x22054), D_ALL);
   848		MMIO_D(_MMIO(0x1a054), D_ALL);
   849	
   850		MMIO_D(_MMIO(0x44070), D_ALL);
   851		MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   852		MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
   853		MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
   854		MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
   855		MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
   856	
   857		MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
   858		MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
   859		MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
   860		MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   861		MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   862		MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   863	
   864		MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   865		MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   866		MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
   867	
   868		MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   869		MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   870		MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   871		MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   872		MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   873		MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   874		MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   875		MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   876		MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   877		MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   878		MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
   879		MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
   880		MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
   881		MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
   882		MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
   883		MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
   884		MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   885	
   886		MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
   887		MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
   888		MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
   889		MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
   890		MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
   891		MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
   892		MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
   893		MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   894		MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   895		MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   896		MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
   897	
   898		MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
   899		MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
   900		MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
   901	
   902		return 0;
   903	}
   904	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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