[PATCH v13 01/10] drm/msm/dpu: set DSC flush bit correctly at MDP CTL flush register

[Marijn Suijten]

On 2023-05-22 17:00:30, Kuogee Hsieh wrote:
> The DSC CTL_FLUSH register should be programmed with the 22th bit

Sorry for botching this in v12 review, there's no DSC CTL_FLUSH
register.  Drop DSC from "The DSC CTL_FLUSH register".

> (DSC_IDX) to flush the DSC hardware blocks, not the literal value of
> 22 (which corresponds to flushing VIG1, VIG2 and RGB1 instead).
> 
> Changes in V12:
> -- split this patch out of "separate DSC flush update out of interface"
> 
> Changes in V13:
> -- rewording the commit text
> 
> Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
> Signed-off-by: Kuogee Hsieh <quic_khsieh at quicinc.com>

Reviewed-by: Marijn Suijten <marijn.suijten at somainline.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 4f7cfa9..69d0ea2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -525,7 +525,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
>  		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
>  			      BIT(cfg->merge_3d - MERGE_3D_0));
>  	if (cfg->dsc) {
> -		DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX);
> +		DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, BIT(DSC_IDX));
>  		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
>  	}
>  }
> -- 
> 2.7.4
>