[RFC PATCH v2 2/5] drm/amd/display: fill up DCN3 DPP color state

[Rodrigo Siqueira Jordao]

On 9/13/23 10:43, Melissa Wen wrote:
> DCN3 DPP color state was uncollected and some state elements from DCN1
> doesn't fit DCN3. Create new elements according to DCN3 color caps and
> fill them up for DTN log output.
> 
> rfc-v2:
> - fix reading of gamcor and blnd gamma states
> 
> Signed-off-by: Melissa Wen <mwen at igalia.com>
> ---
>   .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c  | 45 +++++++++++++++++--
>   drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |  8 ++++
>   2 files changed, 50 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
> index 50dc83404644..a26b33c84ae0 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
> @@ -44,11 +44,50 @@
>   void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
>   {
>   	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
> +	uint32_t gamcor_lut_mode, rgam_lut_mode;
>   
>   	REG_GET(DPP_CONTROL,
> -			DPP_CLOCK_ENABLE, &s->is_enabled);
> -
> -	// TODO: Implement for DCN3
> +		DPP_CLOCK_ENABLE, &s->is_enabled);
> +	// Pre-degamma (ROM)
> +	REG_GET_2(PRE_DEGAM,
> +		  PRE_DEGAM_MODE, &s->pre_dgam_mode,
> +		  PRE_DEGAM_SELECT, &s->pre_dgam_select);

nitpick:
Add a new line before each comment in this function.

> +	// Gamma Correction (RAM)
> +	REG_GET(CM_GAMCOR_CONTROL,
> +		CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode);
> +	if (s->gamcor_mode) {
> +		REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &gamcor_lut_mode);
> +		if (!gamcor_lut_mode)
> +			s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
> +	}
> +	// Shaper LUT (RAM), 3D LUT (mode, bit-depth, size)
> +	REG_GET(CM_SHAPER_CONTROL,
> +		CM_SHAPER_LUT_MODE, &s->shaper_lut_mode);
> +	REG_GET(CM_3DLUT_MODE,
> +		CM_3DLUT_MODE_CURRENT, &s->lut3d_mode);
> +	REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
> +		CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
> +	REG_GET(CM_3DLUT_MODE,
> +		CM_3DLUT_SIZE, &s->lut3d_size);
> +	// Gamut Remap Matrix (3x4)
> +	REG_GET(CM_GAMUT_REMAP_CONTROL,
> +		CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
> +	if (s->gamut_remap_mode) {
> +		s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
> +		s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
> +		s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
> +		s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
> +		s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
> +		s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
> +	}
> +	// Blend/Out Gamma (RAM)
> +	REG_GET(CM_BLNDGAM_CONTROL,
> +		CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode);
> +	if (s->rgam_lut_mode){
> +		REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode);
> +		if (!rgam_lut_mode)
> +			s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
> +	}
>   }
>   /*program post scaler scs block in dpp CM*/
>   void dpp3_program_post_csc(
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
> index f4aa76e02518..1dfe08dc4364 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
> @@ -148,6 +148,14 @@ struct dcn_dpp_state {
>   	uint32_t gamut_remap_c23_c24;
>   	uint32_t gamut_remap_c31_c32;
>   	uint32_t gamut_remap_c33_c34;
> +	uint32_t shaper_lut_mode;
> +	uint32_t lut3d_mode;
> +	uint32_t lut3d_bit_depth;
> +	uint32_t lut3d_size;
> +	uint32_t blnd_lut_mode;
> +	uint32_t pre_dgam_mode;
> +	uint32_t pre_dgam_select;
> +	uint32_t gamcor_mode;
>   };
>   
>   struct CM_bias_params {