Hi Alex,<div><br></div><div>Sorry for the late reply.</div><div>I tried the patch on our mipsel platform, but got the following:</div><div><div>[ 1.335937] [drm] Loading RS780 Microcode</div><div>[ 1.910156] [drm:r600_ring_test] *ERROR* radeon: ring test failed (scratch(0x8504)=0xCAFEDEAD)</div>
<div>[ 1.917968] radeon 0000:01:05.0: disabling GPU acceleration</div><div><br></div><div>The platform is equipped with 1G memory, and the physical address layout is:</div><div> [0-256M] physical memory</div><div> [256M - 4352M] hole</div>
<div> [4352M - ] physical memory</div><div>After applying the patch, the ring buffer BO is allocated at physical address(and is equal to the bus address) near 5G.</div><div><br></div><div>I doubt RS780 fails to access such high bus address?</div>
<div>(I can't validate it on X86+rs780e, since I doesn't have >4G memory at hand, could somebody please to validate it?)</div><div><br></div>BTW, I found radeon_gart_bind() will call pci_map_page(), it hooks to swiotlb_map_page on our platform, which seems allocates and returns dma_addr_t of a new page from pool if not meet dma_mask. Seems a bug, since the BO backed by one set of pages, but mapped to GART was another set of pages?</div>
<div><br></div><div><br></div><div><br></div><div>Regards,</div><div>-- cee1</div><div><br><div class="gmail_quote">2011/10/5 <span dir="ltr"><<a href="mailto:alexdeucher@gmail.com">alexdeucher@gmail.com</a>></span><br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">From: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><br>
<br>
If a card wasn't PCIE, we always set the DMA mask to 32 bits.<br>
This is only applies to the old rage128/r1xx gart block on<br>
early radeon asics (~r1xx-r4xx). Newer PCI and IGP cards<br>
can handle 40 bits just fine.<br>
<br>
Signed-off-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><br>
Cc: Chen Jie <<a href="mailto:chenj@lemote.com">chenj@lemote.com</a>><br>
---<br>
drivers/gpu/drm/radeon/radeon_device.c | 7 ++++---<br>
1 files changed, 4 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c<br>
index b51e157..2c3429d 100644<br>
--- a/drivers/gpu/drm/radeon/radeon_device.c<br>
+++ b/drivers/gpu/drm/radeon/radeon_device.c<br>
@@ -750,14 +750,15 @@ int radeon_device_init(struct radeon_device *rdev,<br>
<br>
/* set DMA mask + need_dma32 flags.<br>
* PCIE - can handle 40-bits.<br>
- * IGP - can handle 40-bits (in theory)<br>
+ * IGP - can handle 40-bits<br>
* AGP - generally dma32 is safest<br>
- * PCI - only dma32<br>
+ * PCI - dma32 for legacy pci gart, 40 bits on newer asics<br>
*/<br>
rdev->need_dma32 = false;<br>
if (rdev->flags & RADEON_IS_AGP)<br>
rdev->need_dma32 = true;<br>
- if (rdev->flags & RADEON_IS_PCI)<br>
+ if ((rdev->flags & RADEON_IS_PCI) &&<br>
+ (rdev->family < CHIP_RS400))<br>
rdev->need_dma32 = true;<br>
<br>
dma_bits = rdev->need_dma32 ? 32 : 40;<br>
<font color="#888888">--<br>
1.7.1.1<br>
<br>
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</font></blockquote></div><br></div>