<div class="gmail_quote">On Sat, Oct 22, 2011 at 12:38, Alex Deucher <span dir="ltr"><<a href="mailto:alexdeucher@gmail.com">alexdeucher@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;"> <div class="im">On Fri, Oct 21, 2011 at 3:29 PM, Jean Delvare <<a href="mailto:jdelvare@suse.de">jdelvare@suse.de</a>> wrote:<br> > Hi Alex,<br> ><br> > On Friday 21 October 2011 08:05:48 pm Alex Deucher wrote:<br> >> On Fri, Oct 21, 2011 at 10:16 AM, Jean Delvare <<a href="mailto:jdelvare@suse.de">jdelvare@suse.de</a>><br> >> > Does anyone know at which speed hardware I2C engines are running<br> >> > the DDC bus on various graphics cards?<br> >><br> >> IIRC, we generally target the radeon hw i2c engines to run at 50 khz.<br> ><br> > Then it doesn't seem unreasonable to try and achieve the same for bit-<br> > banged I2C. That's exactly what my patch is doing.<br> <br> </div>Seems fine to me then. 狢 don't know why we set it so low to begin<br> with, but I'm certainly not an i2c expert.<br></blockquote><div><br>Seems fine for me as well. <br clear="all"></div></div><br>Acked-by: Eugeni Dodonov <<a href="mailto:eugeni.dodonov@intel.com">eugeni.dodonov@intel.com</a>><br> <br>-- <br>Eugeni Dodonov<a href="http://eugeni.dodonov.net/" target="_blank"><br></a><br>