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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - LLVM RV670 regression since R600: Packetize instructions"
href="https://bugs.freedesktop.org/show_bug.cgi?id=64193#c9">Comment # 9</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - LLVM RV670 regression since R600: Packetize instructions"
href="https://bugs.freedesktop.org/show_bug.cgi?id=64193">bug 64193</a>
from <span class="vcard"><a class="email" href="mailto:agd5f@yahoo.com" title="Alex Deucher <agd5f@yahoo.com>"> <span class="fn">Alex Deucher</span></a>
</span></b>
<pre>As mentioned by Vadim on IRC:
it seems many instructions in bytecode generated for RS880 have (incorrect)
OMOD = 2, that is, ALU WORD1 bit 7 is set where it shouldn't be set</pre>
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