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<div class="moz-cite-prefix">On 05/08/2013 22:24, Furquan Shaikh
wrote:<br>
</div>
<blockquote
cite="mid:CAEGmHFHW2RuUrU9kj_ds8iXNfVLe209qPNifNQ-0TzM0Xa+V+g@mail.gmail.com"
type="cite">
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<div style="font-family:arial,sans-serif;font-size:13px">We
tested the submitted patch on several systems here and it
seems to be working fine. So, I'm not sure I understand your
comment. Can you please provide more details?</div>
</div>
</blockquote>
<br>
You check for the bit DP_PLL_FREQ_160MHZ in the register DP_A when
calculating the reference frequence for port A eDP panels (i.e. the
assignement of pipe_config->port_clock). This bit is valid on
port A for ivb, snb & ilk, but not on hsw. Haswell has a
complete new way for assigning the pll to the port. For solid
fastboot support I think we need to support them all (i.e. also the
hdmi wrpll clocks and while at it we might as well write the fdi
dotclock readout code, it should be almost the same as the DP
dotclock computation).<br>
-Daniel<br>
<blockquote
cite="mid:CAEGmHFHW2RuUrU9kj_ds8iXNfVLe209qPNifNQ-0TzM0Xa+V+g@mail.gmail.com"
type="cite">
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<div style="font-family:arial,sans-serif;font-size:13px"><br>
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<div style="font-family:arial,sans-serif;font-size:13px">Thanks,</div>
<div style="font-family:arial,sans-serif;font-size:13px">Furquan</div>
<div class="gmail_extra">
<br>
<br>
<div class="gmail_quote">On Mon, Aug 5, 2013 at 12:24 AM,
Daniel Vetter <span dir="ltr"><<a moz-do-not-send="true"
href="mailto:daniel@ffwll.ch" target="_blank">daniel@ffwll.ch</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb">
<div class="h5">On Thu, Aug 01, 2013 at 02:12:22PM
-0700, Furquan Shaikh wrote:<br>
> Enables getting correct mode clock when reading
pipe config<br>
><br>
> Signed-off-by: Furquan Shaikh <<a
moz-do-not-send="true"
href="mailto:furquan@google.com">furquan@google.com</a>><br>
> ---<br>
> drivers/gpu/drm/i915/intel_ddi.c | 8
++++++++<br>
> drivers/gpu/drm/i915/intel_display.c | 9
++++++++-<br>
> 2 files changed, 16 insertions(+), 1 deletion(-)<br>
><br>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c<br>
> index 931b4bb..fa0af9b 100644<br>
> --- a/drivers/gpu/drm/i915/intel_ddi.c<br>
> +++ b/drivers/gpu/drm/i915/intel_ddi.c<br>
> @@ -1269,6 +1269,7 @@ static void
intel_ddi_get_config(struct intel_encoder *encoder,<br>
> struct drm_i915_private *dev_priv =
encoder->base.dev->dev_private;<br>
> struct intel_crtc *intel_crtc =
to_intel_crtc(encoder->base.crtc);<br>
> enum transcoder cpu_transcoder =
intel_crtc->config.cpu_transcoder;<br>
> + int port =
intel_ddi_get_encoder_port(encoder);<br>
> u32 temp, flags = 0;<br>
><br>
> temp =
I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));<br>
> @@ -1282,6 +1283,13 @@ static void
intel_ddi_get_config(struct intel_encoder *encoder,<br>
> flags |= DRM_MODE_FLAG_NVSYNC;<br>
><br>
> pipe_config->adjusted_mode.flags |=
flags;<br>
> +<br>
> + if (port == PORT_A) {<br>
> + if ((I915_READ(DP_A) &
DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)<br>
> + pipe_config->port_clock
= 162000;<br>
> + else<br>
> + pipe_config->port_clock
= 270000;<br>
> + }<br>
<br>
</div>
</div>
I don't think this works correctly since for DP we have
new clocks on<br>
haswell, see intel_ddi_pll_mode_set. Also I think it'd be
good to go right<br>
ahead and implement clock readout support for all hsw
clock sources, not<br>
just DP.<br>
-Daniel<br>
<div>
<div class="h5"><br>
> }<br>
><br>
> static void intel_ddi_destroy(struct drm_encoder
*encoder)<br>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c<br>
> index 3e66f05..681c99a 100644<br>
> --- a/drivers/gpu/drm/i915/intel_display.c<br>
> +++ b/drivers/gpu/drm/i915/intel_display.c<br>
> @@ -7176,6 +7176,8 @@ static void
i9xx_crtc_clock_get(struct intel_crtc *crtc,<br>
> pipe_config->pixel_multiplier;<br>
> }<br>
><br>
> +#define div_ceil(A, B) ((A)/(B) + ((A)%(B) ? 1 :
0))<br>
> +<br>
> static void ironlake_crtc_clock_get(struct
intel_crtc *crtc,<br>
> struct
intel_crtc_config *pipe_config)<br>
> {<br>
> @@ -7218,7 +7220,11 @@ static void
ironlake_crtc_clock_get(struct intel_crtc *crtc,<br>
> return;<br>
><br>
> clock = ((u64)link_m * (u64)link_freq *
(u64)repeat);<br>
> - do_div(clock, link_n);<br>
> + /* This is required because the value comes
out to be in fraction<br>
> + (eg. 70699.54). Need to round it up
since values are compared in<br>
> + drm_mode_equal<br>
> + */<br>
> + clock = div_ceil(clock, link_n);<br>
><br>
> pipe_config->adjusted_mode.clock =
clock;<br>
> }<br>
> @@ -9588,6 +9594,7 @@ static void
intel_init_display(struct drm_device *dev)<br>
><br>
> if (HAS_DDI(dev)) {<br>
>
dev_priv->display.get_pipe_config =
haswell_get_pipe_config;<br>
> + dev_priv->display.get_clock =
ironlake_crtc_clock_get;<br>
> dev_priv->display.crtc_mode_set
= haswell_crtc_mode_set;<br>
> dev_priv->display.crtc_enable =
haswell_crtc_enable;<br>
> dev_priv->display.crtc_disable =
haswell_crtc_disable;<br>
> --<br>
> 1.8.3<br>
><br>
</div>
</div>
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<span class="HOEnZb"><font color="#888888"><br>
--<br>
Daniel Vetter<br>
Software Engineer, Intel Corporation<br>
<a moz-do-not-send="true"
href="tel:%2B41%20%280%29%2079%20365%2057%2048"
value="+41793655748">+41 (0) 79 365 57 48</a> - <a
moz-do-not-send="true" href="http://blog.ffwll.ch"
target="_blank">http://blog.ffwll.ch</a><br>
</font></span></blockquote>
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