<div dir="ltr"><div><div><br></div>As I mentioned already on internal messenger, you first may need discuss with Rahul Sharma who is preparing hdmiphy patch set.<br><br>The patch set will move all hdmiphy related codes from hdmi to hdmiphy driver. So we may need a separated hdmiphy node, not in hdmi node. And it'd better to move the hdmiphy config data to the hdmiphy driver.<br>
</div><div><div><div><div><div class="gmail_extra"><br></div><div class="gmail_extra">Thanks,<br>Inki Dae<br></div><div class="gmail_extra"><br><div class="gmail_quote">2013/8/13 Shirish S <span dir="ltr"><<a href="mailto:s.shirish@samsung.com" target="_blank">s.shirish@samsung.com</a>></span><br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This patch adds dt support to hdmiphy config settings<br>
as it is board specific and depends on the signal pattern<br>
of board.<br>
<br>
Signed-off-by: Shirish S <<a href="mailto:s.shirish@samsung.com">s.shirish@samsung.com</a>><br>
---<br>
 .../devicetree/bindings/video/exynos_hdmi.txt      |   18 +-<br>
 drivers/gpu/drm/exynos/exynos_hdmi.c               |  191 +++++++-------------<br>
 2 files changed, 80 insertions(+), 129 deletions(-)<br>
<br>
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt<br>
index 323983b..fb8a643 100644<br>
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt<br>
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt<br>
@@ -12,7 +12,11 @@ Required properties:<br>
        a) phandle of the gpio controller node.<br>
        b) pin number within the gpio controller.<br>
        c) optional flags and pull up/down.<br>
-<br>
+- hdmiphy_confs: following information about the hdmiphy conf settings.<br>
+        a) "nr_confs" specifies the number of pixel clocks supported.<br>
+       b) "confX: confX" specifies the phy configuration settings,<br>
+               "clock-frequency" specifies the pixel clock<br>
+               "conf" specifies the setting for the corresponding pixel clock<br>
 Example:<br>
<br>
        hdmi {<br>
@@ -20,4 +24,16 @@ Example:<br>
                reg = <0x14530000 0x100000>;<br>
                interrupts = <0 95 0>;<br>
                hpd-gpio = <&gpx3 7 1>;<br>
+               hdmiphy_confs {<br>
+                       nr_confs = <1>;<br>
+                       conf0: conf0 {<br>
+                               clock-frequency = <25200000>;<br>
+                               conf =  /bits/ 8 <<br>
+                                       0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08<br>
+                                       0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80<br>
+                                       0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86<br>
+                                       0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80<br>
+                               >;<br>
+                       };<br>
+               }<br>
        };<br>
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c<br>
index 2f5c694..cb929ff 100644<br>
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c<br>
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c<br>
@@ -179,6 +179,11 @@ struct hdmi_conf_regs {<br>
        } conf;<br>
 };<br>
<br>
+struct hdmiphy_config {<br>
+       int pixel_clock;<br>
+       u8 conf[32];<br>
+};<br>
+<br>
 struct hdmi_context {<br>
        struct device                   *dev;<br>
        struct drm_device               *drm_dev;<br>
@@ -199,16 +204,14 @@ struct hdmi_context {<br>
<br>
        struct hdmi_resources           res;<br>
<br>
+       struct hdmiphy_config           *confs;<br>
+       int                             nr_confs;<br>
+<br>
        int                             hpd_gpio;<br>
<br>
        enum hdmi_type                  type;<br>
 };<br>
<br>
-struct hdmiphy_config {<br>
-       int pixel_clock;<br>
-       u8 conf[32];<br>
-};<br>
-<br>
 /* list of phy config settings */<br>
 static const struct hdmiphy_config hdmiphy_v13_configs[] = {<br>
        {<br>
@@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {<br>
        },<br>
 };<br>
<br>
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {<br>
-       {<br>
-               .pixel_clock = 25200000,<br>
-               .conf = {<br>
-                       0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,<br>
-                       0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 27000000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,<br>
-                       0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 27027000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,<br>
-                       0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 36000000,<br>
-               .conf = {<br>
-                       0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,<br>
-                       0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 40000000,<br>
-               .conf = {<br>
-                       0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,<br>
-                       0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 65000000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,<br>
-                       0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 74176000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,<br>
-                       0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 74250000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,<br>
-                       0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 83500000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,<br>
-                       0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 106500000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,<br>
-                       0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 108000000,<br>
-               .conf = {<br>
-                       0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,<br>
-                       0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 146250000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,<br>
-                       0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,<br>
-               },<br>
-       },<br>
-       {<br>
-               .pixel_clock = 148500000,<br>
-               .conf = {<br>
-                       0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,<br>
-                       0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,<br>
-                       0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,<br>
-                       0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,<br>
-               },<br>
-       },<br>
-};<br>
-<br>
 struct hdmi_infoframe {<br>
        enum HDMI_PACKET_TYPE type;<br>
        u8 ver;<br>
@@ -777,8 +660,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)<br>
                confs = hdmiphy_v13_configs;<br>
                count = ARRAY_SIZE(hdmiphy_v13_configs);<br>
        } else if (hdata->type == HDMI_TYPE14) {<br>
-               confs = hdmiphy_v14_configs;<br>
-               count = ARRAY_SIZE(hdmiphy_v14_configs);<br>
+               confs = hdata->confs;<br>
+               count = hdata->nr_confs;<br>
        } else<br>
                return -EINVAL;<br>
<br>
@@ -1365,7 +1248,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)<br>
        if (hdata->type == HDMI_TYPE13)<br>
                hdmiphy_data = hdmiphy_v13_configs[i].conf;<br>
        else<br>
-               hdmiphy_data = hdmiphy_v14_configs[i].conf;<br>
+               hdmiphy_data = hdata->confs[i].conf;<br>
<br>
        memcpy(buffer, hdmiphy_data, 32);<br>
        ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);<br>
@@ -1885,6 +1768,51 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata<br>
 err_data:<br>
        return NULL;<br>
 }<br>
+<br>
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,<br>
+                                               struct hdmi_context *hdata)<br>
+{<br>
+       struct device *dev = &pdev->dev;<br>
+       struct device_node *dev_np = dev->of_node;<br>
+       struct device_node *phy_conf, *cfg_np;<br>
+       int i = 0;<br>
+<br>
+       phy_conf = of_find_node_by_name(dev_np, "hdmiphy_confs");<br>
+       if (phy_conf == NULL) {<br>
+               DRM_ERROR("Did not find hdmiphy_conf node\n");<br>
+               return -ENODEV;<br>
+       }<br>
+<br>
+       of_property_read_u32(phy_conf, "nr_confs", &hdata->nr_confs);<br>
+       hdata->confs = kzalloc((hdata->nr_confs * sizeof<br>
+                                       (struct hdmiphy_config)), GFP_KERNEL);<br>
+<br>
+       for_each_child_of_node(phy_conf, cfg_np) {<br>
+               if (!of_find_property(cfg_np, "clock-frequency", NULL))<br>
+                       continue;<br>
+<br>
+               if (of_property_read_u32_array(cfg_np, "clock-frequency",<br>
+                                       (u32 *)&hdata->confs[i].<br>
+                                                       pixel_clock, 1)) {<br>
+                               DRM_ERROR("Failed to get pixel clock\n");<br>
+                               return -EINVAL;<br>
+               }<br>
+<br>
+               /*<br>
+                * conf property holds the phy setting value<br>
+                * for a particular board<br>
+                */<br>
+               if (of_property_read_u8_array(cfg_np, "conf",<br>
+                                       (u8 *)&hdata->confs[i].conf, 32)) {<br>
+                               DRM_ERROR("Failed to get conf\n");<br>
+                               return -EINVAL;<br>
+               }<br>
+               i++;<br>
+       }<br>
+       return 0;<br>
+<br>
+}<br>
+<br>
 #else<br>
 static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata<br>
                                        (struct device *dev)<br>
@@ -2038,6 +1966,13 @@ static int hdmi_probe(struct platform_device *pdev)<br>
                goto err_hdmiphy;<br>
        }<br>
<br>
+       /* get hdmiphy confs */<br>
+       ret = drm_hdmi_dt_parse_phy_conf(pdev, hdata);<br>
+       if (ret) {<br>
+               DRM_ERROR("failed to get confs\n");<br>
+               goto err_hdmiphy;<br>
+       }<br>
+<br>
        /* Attach HDMI Driver to common hdmi. */<br>
        exynos_hdmi_drv_attach(drm_hdmi_ctx);<br>
<span class="HOEnZb"><font color="#888888"><br>
--<br>
1.7.10.4<br>
<br>
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</font></span></blockquote></div><br></div></div></div></div></div></div>