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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [AMD Fusion E-350] HDMI refresh rates doesn't match expectations"
href="https://bugs.freedesktop.org/show_bug.cgi?id=76564#c14">Comment # 14</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [AMD Fusion E-350] HDMI refresh rates doesn't match expectations"
href="https://bugs.freedesktop.org/show_bug.cgi?id=76564">bug 76564</a>
from <span class="vcard"><a class="email" href="mailto:agd5f@yahoo.com" title="Alex Deucher <agd5f@yahoo.com>"> <span class="fn">Alex Deucher</span></a>
</span></b>
<pre>(In reply to <a href="show_bug.cgi?id=76564#c13">comment #13</a>)
<span class="quote">> Do the PLL values in the log files I posted indicate a problem, or are they
> okay?</span >
[drm:radeon_compute_pll_avivo], 14875, pll dividers - fb: 23.8 ref: 2, post 8
[drm:radeon_compute_pll_avivo], 7406, pll dividers - fb: 23.7 ref: 2, post 16
The display pll looks fine to me. The clock formula is:
pixel_clock = (reference_frequency * feedback_divider) / (reference_divider *
post_divider)
The reference frequency is 100 Mhz, so:
(100Mhz * 23.8) / (2 * 8) = 148.75Mhz
(100Mhz * 23.7) / (2 * 16) = 74.0625Mhz
<span class="quote">>
> How can you see the PLL values fglrx is using?</span >
You'd need to dump the PLL registers using radeonreg
(<a href="http://cgit.freedesktop.org/~airlied/radeontool/">http://cgit.freedesktop.org/~airlied/radeontool/</a>).
PPLL1
0x400 - ref div - bits 9:0
0x404 - fb div - whole part bits 26:16, fractional part bits 3:0
0x408 - post div - bits 6:0
PPLL2
0x440 - ref div - bits 9:0
0x444 - fb div - whole part bits 26:16, fractional part bits 3:0
0x448 - post div - bits 6:0
e.g., ./radeonreg regmatch 0x400</pre>
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