<div dir="ltr">On Thu, Mar 20, 2014 at 6:06 PM, Arthur Borsboom <<a href="mailto:arthurborsboom@gmail.com" target="_blank">arthurborsboom@gmail.com</a>> wrote: <div class="gmail_extra"><div class="gmail_quote"> <blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Mainly styling fixes of inline documentation Signed-off-by: Arthur Borsboom <<a href="mailto:arthurborsboom@gmail.com">arthurborsboom@gmail.com</a>> </blockquote><div> </div><div>Hi Arthur </div><div>I'm not a code style fanatic, but I see a bunch of problems with this patch. If you're going through the hassle of changing stuff in accordance to CodingStyle, you at least need to make sure you're actually following it. </div><div>Maybe this should go through the kernel janitors or kernel newbies mailing lists first. </div><div>Cheers Patrik </div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> --- drivers/gpu/drm/gma500/framebuffer.c | 36 ++-- drivers/gpu/drm/gma500/psb_intel_display.c | 35 ++-- drivers/gpu/drm/gma500/psb_intel_reg.h | 259 +++++++++++++---------------- drivers/gpu/drm/gma500/psb_irq.c | 64 +++---- 4 files changed, 181 insertions(+), 213 deletions(-) diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index e7fcc14..0dd015a 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -103,8 +103,10 @@ static int psbfb_pan(struct fb_var_screeninfo *var, struct fb_info *info) * the actual fb is mapped. In our case that isn't quite true. */ if (psbfb->gtt->npage) { - /* GTT roll shifts in 4K pages, we need to shift the right - number of pages */ + /* + * GTT roll shifts in 4K pages, we need to shift the right + number of pages + */ int pages = info->fix.line_length >> 12; psb_gtt_roll(dev, psbfb->gtt, var->yoffset * pages); } @@ -229,7 +231,7 @@ static struct fb_ops psbfb_unaccel_ops = { .fb_ioctl = psbfb_ioctl, }; -/** +/* * psb_framebuffer_init - initialize a framebuffer * @dev: our DRM device * @fb: framebuffer to set up @@ -270,7 +272,7 @@ static int psb_framebuffer_init(struct drm_device *dev, return 0; } -/** +/* * psb_framebuffer_create - create a framebuffer backed by gt * @dev: our DRM device * @mode_cmd: the description of the requested mode @@ -302,7 +304,7 @@ static struct drm_framebuffer *psb_framebuffer_create return &fb->base; } -/** +/* * psbfb_alloc - allocate frame buffer memory * @dev: the DRM device * @aligned_size: space needed @@ -327,7 +329,7 @@ static struct gtt_range *psbfb_alloc(struct drm_device *dev, int aligned_size) return NULL; } -/** +/* * psbfb_create - create a framebuffer * @fbdev: the framebuffer device * @sizes: specification of the layout @@ -386,9 +388,9 @@ static int psbfb_create(struct psb_fbdev *fbdev, if (backing == NULL) { /* - * We couldn't get the space we wanted, fall back to the - * display engine requirement instead. The HW requires - * the pitch to be 64 byte aligned + * We couldn't get the space we wanted, fall back to the + * display engine requirement instead. The HW requires + * the pitch to be 64 byte aligned */ gtt_roll = 0; /* Don't use GTT accelerated scrolling */ @@ -489,7 +491,7 @@ out_err1: return ret; } -/** +/* * psb_user_framebuffer_create - create framebuffer * @dev: our DRM device * @filp: client file @@ -549,9 +551,11 @@ static int psbfb_probe(struct drm_fb_helper *helper, if (bytespp == 3) /* no 24bit packed */ bytespp = 4; - /* If the mode will not fit in 32bit then switch to 16bit to get + /* + * If the mode will not fit in 32bit then switch to 16bit to get a console on full resolution. The X mode setting server will - allocate its own 32bit GEM framebuffer */ + allocate its own 32bit GEM framebuffer + */ if (ALIGN(sizes->fb_width * bytespp, 64) * sizes->fb_height > dev_priv->vram_stolen_size) { sizes->surface_bpp = 16; @@ -633,7 +637,7 @@ static void psbfb_output_poll_changed(struct drm_device *dev) drm_fb_helper_hotplug_event(&fbdev->psb_fb_helper); } -/** +/* * psb_user_framebuffer_create_handle - add hamdle to a framebuffer * @fb: framebuffer * @file_priv: our DRM file @@ -652,7 +656,7 @@ static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb, return drm_gem_handle_create(file_priv, &r->gem, handle); } -/** +/* * psb_user_framebuffer_destroy - destruct user created fb * @fb: framebuffer * @@ -666,7 +670,7 @@ static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb) /* Let DRM do its clean up */ drm_framebuffer_cleanup(fb); - /* We are no longer using the resource in GEM */ + /* We are no longer using the resource in GEM */ drm_gem_object_unreference_unlocked(&r->gem); kfree(fb); } @@ -761,7 +765,7 @@ void psb_modeset_init(struct drm_device *dev) dev->mode_config.funcs = &psb_mode_funcs; /* set memory base */ - /* Oaktrail and Poulsbo should use BAR 2*/ + /* Oaktrail and Poulsbo should use BAR 2 */ pci_read_config_dword(dev->pdev, PSB_BSM, (u32 *) &(dev->mode_config.fb_base)); diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c index 21aed85..b11cbd6 100644 --- a/drivers/gpu/drm/gma500/psb_intel_display.c +++ b/drivers/gpu/drm/gma500/psb_intel_display.c @@ -1,5 +1,5 @@ /* - * Copyright ÂŠ 2006-2011 Intel Corporation + * Copyright Š 2006-2011 Intel Corporation * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -53,7 +53,8 @@ static const struct gma_limit_t psb_intel_limits[] = { .m2 = {.min = 3, .max = 7}, .p = {.min = 7, .max = 98}, .p1 = {.min = 1, .max = 8}, - /* The single-channel range is 25-112Mhz, and dual-channel + /* + * The single-channel range is 25-112Mhz, and dual-channel * is 80-224Mhz. Prefer single channel as much as possible. */ .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7}, @@ -81,7 +82,7 @@ static void psb_intel_clock(int refclk, struct gma_clock_t *clock) clock->dot = clock->vco / clock->p; } -/** +/* * Return the pipe currently connected to the panel fitter, * or -1 if the panel fitter is not present or not in use */ @@ -226,7 +227,8 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, udelay(150); } - /* The LVDS pin pair needs to be on before the DPLLs are enabled. + /* + * The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. */ @@ -238,7 +240,8 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, lvds |= LVDS_PIPEB_SELECT; lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; - /* Set the B0-B3 data pairs corresponding to + /* + * Set the B0-B3 data pairs corresponding to * whether we're going to * set the DPLLs for dual-channel mode or not. */ @@ -246,7 +249,8 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, if (clock.p2 == 7) lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; - /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) + /* + * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) * appropriately here, but we need to look more * thoroughly into how panels behave in the two modes. */ @@ -261,7 +265,7 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, /* Wait for the clocks to stabilize. */ udelay(150); - /* write it again -- the BIOS does, after all */ + /* Write it again -- the BIOS does, after all */ REG_WRITE(map->dpll, dpll); REG_READ(map->dpll); @@ -280,7 +284,8 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, ((adjusted_mode->crtc_vblank_end - 1) << 16)); REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); - /* pipesrc and dspsize control the size that is scaled from, + /* + * pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. */ REG_WRITE(map->size, @@ -371,7 +376,8 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev, psb_intel_clock(48000, &clock); } - /* XXX: It would be nice to validate the clocks, but we can't reuse + /* + * XXX: It would be nice to validate the clocks, but we can't reuse * i830PllIsValid() because it relies on the xf86_config connector * configuration being accurate, which it isn't necessarily. */ @@ -379,7 +385,7 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev, return clock.dot; } -/** Returns the currently programmed mode of the given pipe. */ +/* Returns the currently programmed mode of the given pipe. */ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, struct drm_crtc *crtc) { @@ -466,7 +472,8 @@ static void psb_intel_cursor_init(struct drm_device *dev, struct gtt_range *cursor_gt; if (dev_priv->ops->cursor_needs_phys) { - /* Allocate 4 pages of stolen mem for a hardware cursor. That + /* + * Allocate 4 pages of stolen mem for a hardware cursor. That * is enough for the 64 x 64 ARGB cursors we support. */ cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1, @@ -495,8 +502,10 @@ void psb_intel_crtc_init(struct drm_device *dev, int pipe, int i; uint16_t *r_base, *g_base, *b_base; - /* We allocate a extra array of drm_connector pointers - * for fbdev after the crtc */ + /* + * We allocate an extra array of drm_connector pointers + * for fbdev after the crtc + */ gma_crtc = kzalloc(sizeof(struct gma_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h index 0be30e4..ec32a06 100644 --- a/drivers/gpu/drm/gma500/psb_intel_reg.h +++ b/drivers/gpu/drm/gma500/psb_intel_reg.h @@ -17,9 +17,7 @@ #ifndef __PSB_INTEL_REG_H__ #define __PSB_INTEL_REG_H__ -/* - * GPIO regs - */ +/* GPIO regs */ #define GPIOA 0x5010 #define GPIOB 0x5014 #define GPIOC 0x5018 @@ -254,7 +252,7 @@ #define DPLL_LOCK (1 << 15) /* CDV */ /* - * The i830 generation, in DAC/serial mode, defines p1 as two plus this + * The i830 generation, in DAC/serial mode, defines p1 as two plus this * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. */ # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 @@ -292,9 +290,7 @@ #define SDVO_MULTIPLIER_SHIFT_HIRES 4 #define SDVO_MULTIPLIER_SHIFT_VGA 0 -/* - * PLL_MD - */ +/* PLL_MD */ /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ #define DPLL_A_MD 0x0601c /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ @@ -385,7 +381,7 @@ #define TV_HOTPLUG_INT_EN (1 << 18) #define CRT_HOTPLUG_INT_EN (1 << 9) #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) -/* CDV.. */ +/* CDV */ #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) @@ -419,7 +415,7 @@ #define SDVO_COLOR_RANGE_16_235 (1 << 8) #define SDVO_AUDIO_ENABLE (1 << 6) -/** +/* * 915G/GM SDVO pixel multiplier. * * Programmed value is multiplier - 1, up to 5x. @@ -702,9 +698,7 @@ struct dpst_guardband { #define VGA_2X_MODE (1 << 30) #define VGA_PIPE_B_SELECT (1 << 29) -/* - * Overlay registers - */ +/* Overlay registers */ #define OV_C_OFFSET 0x08000 #define OV_OVADD 0x30000 #define OV_DOVASTA 0x30008 @@ -739,9 +733,7 @@ struct dpst_guardband { #define SWF5 0x71424 #define SWF6 0x71428 -/* - * 855 scratch registers. - */ +/* 855 scratch registers */ #define SWF00 0x70410 #define SWF01 0x70414 #define SWF02 0x70418 @@ -762,10 +754,7 @@ struct dpst_guardband { #define SWF31 0x72418 #define SWF32 0x7241c - -/* - * Palette registers - */ +/* Palette registers */ #define PALETTE_A 0x0a000 #define PALETTE_B 0x0a800 #define PALETTE_C 0x0ac00 @@ -789,17 +778,13 @@ struct dpst_guardband { #define CURCBASE 0x700e4 #define CURCPOS 0x700e8 -/* - * Interrupt Registers - */ +/* Interrupt Registers */ #define IER 0x020a0 #define IIR 0x020a4 #define IMR 0x020a8 #define ISR 0x020ac -/* - * MOORESTOWN delta registers - */ +/* MOORESTOWN delta registers */ #define MRST_DPLL_A 0x0f014 #define MDFLD_DPLL_B 0x0f018 #define MDFLD_INPUT_REF_SEL (1 << 14) @@ -814,9 +799,7 @@ struct dpst_guardband { #define MDFLD_DPLL_DIV1 0x0f04c #define MRST_PERF_MODE 0x020f4 -/* - * MEDFIELD HDMI registers - */ +/* MEDFIELD HDMI registers */ #define HDMIPHYMISCCTL 0x61134 #define HDMI_PHY_POWER_DOWN 0x7f #define HDMIB_CONTROL 0x61140 @@ -862,13 +845,9 @@ struct dpst_guardband { #define MRST_DSPBBASE 0x7119c #define MDFLD_DSPCBASE 0x7219c -/* - * Moorestown registers. - */ +/* Moorestown registers */ -/* - * MIPI IP registers - */ +/* MIPI IP registers */ #define MIPIC_REG_OFFSET 0x800 #define DEVICE_READY_REG 0xb000 @@ -998,9 +977,7 @@ struct dpst_guardband { #define DBI_BW_CTRL_REG 0xb084 #define CLK_LANE_SWT_REG 0xb088 -/* - * MIPI Adapter registers - */ +/* MIPI Adapter registers */ #define MIPI_CONTROL_REG 0xb104 #define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1)) #define MIPI_DATA_ADDRESS_REG 0xb108 @@ -1020,161 +997,149 @@ struct dpst_guardband { /* DBI COMMANDS */ #define soft_reset 0x01 /* - * The display module performs a software reset. - * Registers are written with their SW Reset default values. + * The display module performs a software reset. + * Registers are written with their SW Reset default values. */ #define get_power_mode 0x0a -/* - * The display module returns the current power mode - */ +/* The display module returns the current power mode */ #define get_address_mode 0x0b -/* - * The display module returns the current status. - */ +/* The display module returns the current status */ #define get_pixel_format 0x0c /* - * This command gets the pixel format for the RGB image data - * used by the interface. + * This command gets the pixel format for the RGB image data + * used by the interface. */ #define get_display_mode 0x0d -/* - * The display module returns the Display Image Mode status. - */ +/* The display module returns the Display Image Mode status */ #define get_signal_mode 0x0e -/* - * The display module returns the Display Signal Mode. - */ +/* The display module returns the Display Signal Mode */ #define get_diagnostic_result 0x0f /* - * The display module returns the self-diagnostic results following - * a Sleep Out command. + * The display module returns the self-diagnostic results following + * a Sleep Out command. */ #define enter_sleep_mode 0x10 /* - * This command causes the display module to enter the Sleep mode. - * In this mode, all unnecessary blocks inside the display module are - * disabled except interface communication. This is the lowest power - * mode the display module supports. + * This command causes the display module to enter the Sleep mode. + * In this mode, all unnecessary blocks inside the display module are + * disabled except interface communication. This is the lowest power + * mode the display module supports. */ #define exit_sleep_mode 0x11 /* - * This command causes the display module to exit Sleep mode. - * All blocks inside the display module are enabled. + * This command causes the display module to exit Sleep mode. + * All blocks inside the display module are enabled. */ #define enter_partial_mode 0x12 /* - * This command causes the display module to enter the Partial Display - * Mode. The Partial Display Mode window is described by the - * set_partial_area command. + * This command causes the display module to enter the Partial Display + * Mode. The Partial Display Mode window is described by the + * set_partial_area command. */ #define enter_normal_mode 0x13 /* - * This command causes the display module to enter the Normal mode. - * Normal Mode is defined as Partial Display mode and Scroll mode are off + * This command causes the display module to enter the Normal mode. + * Normal Mode is defined as Partial Display mode and Scroll mode are off */ #define exit_invert_mode 0x20 /* - * This command causes the display module to stop inverting the image - * data on the display device. The frame memory contents remain unchanged. - * No status bits are changed. + * This command causes the display module to stop inverting the image + * data on the display device. The frame memory contents remain unchanged. + * No status bits are changed. */ #define enter_invert_mode 0x21 /* - * This command causes the display module to invert the image data only on - * the display device. The frame memory contents remain unchanged. - * No status bits are changed. + * This command causes the display module to invert the image data only on + * the display device. The frame memory contents remain unchanged. + * No status bits are changed. */ #define set_gamma_curve 0x26 /* - * This command selects the desired gamma curve for the display device. - * Four fixed gamma curves are defined in section DCS spec. + * This command selects the desired gamma curve for the display device. + * Four fixed gamma curves are defined in section DCS spec. */ #define set_display_off 0x28 -/* ************************************************************************* *\ -This command causes the display module to stop displaying the image data -on the display device. The frame memory contents remain unchanged. -No status bits are changed. -\* ************************************************************************* */ +/* + * This command causes the display module to stop displaying the image data + * on the display device. The frame memory contents remain unchanged. + * No status bits are changed. + */ #define set_display_on 0x29 -/* ************************************************************************* *\ -This command causes the display module to start displaying the image data -on the display device. The frame memory contents remain unchanged. -No status bits are changed. -\* ************************************************************************* */ +/* + * This command causes the display module to start displaying the image data + * on the display device. The frame memory contents remain unchanged. + * No status bits are changed. + */ #define set_column_address 0x2a /* - * This command defines the column extent of the frame memory accessed by - * the hostprocessor with the read_memory_continue and - * write_memory_continue commands. - * No status bits are changed. + * This command defines the column extent of the frame memory accessed by + * the hostprocessor with the read_memory_continue and + * write_memory_continue commands. + * No status bits are changed. */ #define set_page_addr 0x2b /* - * This command defines the page extent of the frame memory accessed by - * the host processor with the write_memory_continue and - * read_memory_continue command. - * No status bits are changed. + * This command defines the page extent of the frame memory accessed by + * the host processor with the write_memory_continue and + * read_memory_continue command. + * No status bits are changed. */ #define write_mem_start 0x2c /* - * This command transfers image data from the host processor to the - * display modules frame memory starting at the pixel location specified - * by preceding set_column_address and set_page_address commands. + * This command transfers image data from the host processor to the + * display modules frame memory starting at the pixel location specified + * by preceding set_column_address and set_page_address commands. */ #define set_partial_area 0x30 /* - * This command defines the Partial Display mode s display area. - * There are two parameters associated with this command, the first - * defines the Start Row (SR) and the second the End Row (ER). SR and ER - * refer to the Frame Memory Line Pointer. + * This command defines the Partial Display mode s display area. + * There are two parameters associated with this command, the first + * defines the Start Row (SR) and the second the End Row (ER). SR and ER + * refer to the Frame Memory Line Pointer. */ #define set_scroll_area 0x33 -/* - * This command defines the display modules Vertical Scrolling Area. - */ +/* This command defines the display modules Vertical Scrolling Area. */ #define set_tear_off 0x34 /* - * This command turns off the display modules Tearing Effect output - * signal on the TE signal line. + * This command turns off the display modules Tearing Effect output + * signal on the TE signal line. */ #define set_tear_on 0x35 /* - * This command turns on the display modules Tearing Effect output signal - * on the TE signal line. + * This command turns on the display modules Tearing Effect output signal + * on the TE signal line. */ #define set_address_mode 0x36 /* - * This command sets the data order for transfers from the host processor - * to display modules frame memory,bits B[7:5] and B3, and from the - * display modules frame memory to the display device, bits B[2:0] and B4. + * This command sets the data order for transfers from the host processor + * to display modules frame memory,bits B[7:5] and B3, and from the + * display modules frame memory to the display device, bits B[2:0] and B4. */ #define set_scroll_start 0x37 /* - * This command sets the start of the vertical scrolling area in the frame - * memory. The vertical scrolling area is fully defined when this command - * is used with the set_scroll_area command The set_scroll_start command - * has one parameter, the Vertical Scroll Pointer. The VSP defines the - * line in the frame memory that is written to the display device as the - * first line of the vertical scroll area. + * This command sets the start of the vertical scrolling area in the frame + * memory. The vertical scrolling area is fully defined when this command + * is used with the set_scroll_area command The set_scroll_start command + * has one parameter, the Vertical Scroll Pointer. The VSP defines the + * line in the frame memory that is written to the display device as the + * first line of the vertical scroll area. */ #define exit_idle_mode 0x38 -/* - * This command causes the display module to exit Idle mode. - */ +/* This command causes the display module to exit Idle mode. */ #define enter_idle_mode 0x39 /* - * This command causes the display module to enter Idle Mode. - * In Idle Mode, color expression is reduced. Colors are shown on the - * display device using the MSB of each of the R, G and B color - * components in the frame memory + * This command causes the display module to enter Idle Mode. + * In Idle Mode, color expression is reduced. Colors are shown on the + * display device using the MSB of each of the R, G and B color + * components in the frame memory */ #define set_pixel_format 0x3a /* - * This command sets the pixel format for the RGB image data used by the - * interface. - * Bits D[6:4] DPI Pixel Format Definition - * Bits D[2:0] DBI Pixel Format Definition - * Bits D7 and D3 are not used. + * This command sets the pixel format for the RGB image data used by the + * interface. + * Bits D[6:4] DPI Pixel Format Definition + * Bits D[2:0] DBI Pixel Format Definition + * Bits D7 and D3 are not used. */ #define DCS_PIXEL_FORMAT_3bpp 0x1 #define DCS_PIXEL_FORMAT_8bpp 0x2 @@ -1186,23 +1151,23 @@ No status bits are changed. #define write_mem_cont 0x3c /* - * This command transfers image data from the host processor to the - * display module's frame memory continuing from the pixel location - * following the previous write_memory_continue or write_memory_start - * command. + * This command transfers image data from the host processor to the + * display module's frame memory continuing from the pixel location + * following the previous write_memory_continue or write_memory_start + * command. */ #define set_tear_scanline 0x44 /* - * This command turns on the display modules Tearing Effect output signal - * on the TE signal line when the display module reaches line N. + * This command turns on the display modules Tearing Effect output signal + * on the TE signal line when the display module reaches line N. */ #define get_scanline 0x45 /* - * The display module returns the current scanline, N, used to update the - * display device. The total number of scanlines on a display device is - * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as - * the first line of V Sync and is denoted as Line 0. - * When in Sleep Mode, the value returned by get_scanline is undefined. + * The display module returns the current scanline, N, used to update the + * display device. The total number of scanlines on a display device is + * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as + * the first line of V Sync and is denoted as Line 0. + * When in Sleep Mode, the value returned by get_scanline is undefined. */ /* MCS or Generic COMMANDS */ @@ -1404,7 +1369,8 @@ No status bits are changed. #define DP_VOLTAGE_MASK (7 << 25) #define DP_VOLTAGE_SHIFT 25 -/* Signal pre-emphasis levels, like voltages, the other end tells us what +/* + * Signal pre-emphasis levels, like voltages, the other end tells us what * they want */ #define DP_PRE_EMPHASIS_0 (0 << 22) @@ -1423,29 +1389,30 @@ No status bits are changed. /* Mystic DPCD version 1.1 special mode */ #define DP_ENHANCED_FRAMING (1 << 18) -/** locked once port is enabled */ +/* locked once port is enabled */ #define DP_PORT_REVERSAL (1 << 15) -/** sends the clock on lane 15 of the PEG for debug */ +/* sends the clock on lane 15 of the PEG for debug */ #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) #define DP_SCRAMBLING_DISABLE (1 << 12) #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) -/** limit RGB values to avoid confusing TVs */ +/* limit RGB values to avoid confusing TVs */ #define DP_COLOR_RANGE_16_235 (1 << 8) -/** Turn on the audio link */ +/* Turn on the audio link */ #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) -/** vs and hs sync polarity */ +/* vs and hs sync polarity */ #define DP_SYNC_VS_HIGH (1 << 4) #define DP_SYNC_HS_HIGH (1 << 3) -/** A fantasy */ +/* A fantasy */ #define DP_DETECTED (1 << 2) -/** The aux channel provides a way to talk to the +/* + * The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported * is 20 bytes in each direction, hence the 5 fixed * data registers diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c index 624eb36..ba3fd4f 100644 --- a/drivers/gpu/drm/gma500/psb_irq.c +++ b/drivers/gpu/drm/gma500/psb_irq.c @@ -19,8 +19,6 @@ * develop this driver. * **************************************************************************/ -/* - */ #include <drm/drmP.h> #include "psb_drv.h" @@ -30,10 +28,7 @@ #include "psb_irq.h" #include "mdfld_output.h" -/* - * inline functions - */ - +/* inline functions */ static inline u32 psb_pipestat(int pipe) { @@ -139,10 +134,7 @@ static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe) } } -/** - * Display controller interrupt handler for pipe event. - * - */ +/* Display controller interrupt handler for pipe event */ static void mid_pipe_event_handler(struct drm_device *dev, int pipe) { struct drm_psb_private *dev_priv = @@ -163,8 +155,10 @@ static void mid_pipe_event_handler(struct drm_device *dev, int pipe) spin_unlock(&dev_priv->irqmask_lock); - /* Clear the 2nd level interrupt status bits - * Sometimes the bits are very sticky so we repeat until they unstick */ + /* + * Clear the 2nd level interrupt status bits + * Sometimes the bits are very sticky so we repeat until they unstick + */ for (i = 0; i < 0xffff; i++) { PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status; @@ -185,9 +179,7 @@ static void mid_pipe_event_handler(struct drm_device *dev, int pipe) drm_handle_vblank(dev, pipe); } -/* - * Display controller interrupt handler. - */ +/* Display controller interrupt handler */ static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) { if (vdc_stat & _PSB_IRQ_ASLE) @@ -200,9 +192,7 @@ static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) mid_pipe_event_handler(dev, 1); } -/* - * SGX interrupt handler - */ +/* SGX interrupt handler */ static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2) { struct drm_psb_private *dev_priv = dev->dev_private; @@ -267,7 +257,8 @@ irqreturn_t psb_irq_handler(int irq, void *arg) if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE)) dsp_int = 1; - /* FIXME: Handle Medfield + /* + * FIXME: Handle Medfield if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) dsp_int = 1; */ @@ -292,8 +283,10 @@ irqreturn_t psb_irq_handler(int irq, void *arg) handled = 1; } - /* Note: this bit has other meanings on some devices, so we will - need to address that later if it ever matters */ + /* + * Note: this bit has other meanings on some devices, so we will + need to address that later if it ever matters + */ if (hotplug_int && dev_priv->ops->hotplug) { handled = dev_priv->ops->hotplug(dev); REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); @@ -336,7 +329,7 @@ void psb_irq_preinstall(struct drm_device *dev) dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG; */ - /* Revisit this area - want per device masks ? */ + /* TODO: Revisit this area - want per device masks ? */ if (dev_priv->ops->hotplug) dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC; dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG; @@ -461,7 +454,7 @@ int psb_irq_enable_dpst(struct drm_device *dev) spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); - /* enable DPST */ + /* Enable DPST */ mid_enable_pipe_event(dev_priv, 0); psb_irq_turn_on_dpst(dev); @@ -507,9 +500,7 @@ int psb_irq_disable_dpst(struct drm_device *dev) return 0; } -/* - * It is used to enable VBLANK interrupt - */ +/* It is used to enable VBLANK interrupt */ int psb_enable_vblank(struct drm_device *dev, int pipe) { struct drm_psb_private *dev_priv = dev->dev_private; @@ -517,8 +508,10 @@ int psb_enable_vblank(struct drm_device *dev, int pipe) uint32_t reg_val = 0; uint32_t pipeconf_reg = mid_pipeconf(pipe); - /* Medfield is different - we should perhaps extract out vblank - and blacklight etc ops */ + /* + * Medfield is different - we should perhaps extract out vblank + * and blacklight etc ops + */ if (IS_MFLD(dev)) return mdfld_enable_te(dev, pipe); @@ -546,9 +539,7 @@ int psb_enable_vblank(struct drm_device *dev, int pipe) return 0; } -/* - * It is used to disable VBLANK interrupt - */ +/* It is used to disable VBLANK interrupt */ void psb_disable_vblank(struct drm_device *dev, int pipe) { struct drm_psb_private *dev_priv = dev->dev_private; @@ -570,9 +561,7 @@ void psb_disable_vblank(struct drm_device *dev, int pipe) spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); } -/* - * It is used to enable TE interrupt - */ +/* It is used to enable TE interrupt */ int mdfld_enable_te(struct drm_device *dev, int pipe) { struct drm_psb_private *dev_priv = @@ -599,9 +588,7 @@ int mdfld_enable_te(struct drm_device *dev, int pipe) return 0; } -/* - * It is used to disable TE interrupt - */ +/* It is used to disable TE interrupt */ void mdfld_disable_te(struct drm_device *dev, int pipe) { struct drm_psb_private *dev_priv = @@ -619,7 +606,8 @@ void mdfld_disable_te(struct drm_device *dev, int pipe) spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); } -/* Called from drm generic code, passed a 'crtc', which +/* + * Called from drm generic code, passed a 'crtc', which * we use as a pipe index */ u32 psb_get_vblank_counter(struct drm_device *dev, int pipe) -- 1.9.0 </blockquote></div> </div></div>