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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [bisected] moving moire starting with "drm/radeon: improve PLL params if we don't match exactly v2""
href="https://bugs.freedesktop.org/show_bug.cgi?id=77673#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [bisected] moving moire starting with "drm/radeon: improve PLL params if we don't match exactly v2""
href="https://bugs.freedesktop.org/show_bug.cgi?id=77673">bug 77673</a>
from <span class="vcard"><a class="email" href="mailto:agd5f@yahoo.com" title="Alex Deucher <agd5f@yahoo.com>"> <span class="fn">Alex Deucher</span></a>
</span></b>
<pre>(In reply to <a href="show_bug.cgi?id=77673#c3">comment #3</a>)
<span class="quote">> Looks like the new pll computation is not respecting the
> RADEON_PLL_USE_FRAC_FB_DIV flag. Older asics shouldn't use fraction fb
> dividers.</span >
Nevermind, we always set the RADEON_PLL_USE_FRAC_FB_DIV for LVDS if spread
spectrum is enabled. Looks like we aren't respecting RADEON_PLL_USE_REF_DIV
properly.</pre>
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