<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, May 26, 2014 at 2:35 AM, Thierry Reding <span dir="ltr"><<a href="mailto:treding@nvidia.com" target="_blank">treding@nvidia.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">On Mon, May 26, 2014 at 11:28:42AM +0200, Stéphane Marchesin wrote:<br>
<div class="">><br>
><br>
><br>
> On Mon, May 26, 2014 at 2:07 AM, Lucas Stach <<a href="mailto:l.stach@pengutronix.de">l.stach@pengutronix.de</a><mailto:<a href="mailto:l.stach@pengutronix.de">l.stach@pengutronix.de</a>>> wrote:<br>
> > Am Freitag, den 23.05.2014, 18:58 -0700 schrieb Stéphane Marchesin:<br>
> > > The current code doesn't enable the EMC clock, without which the<br>
> > > display cannot function, so let's enable this clock. We also need a<br>
> > > bit of code to pick the right frequency for the EMC clock depending<br>
> > > on the current video mode settings.<br>
> > ><br>
> > That's not the right way to do it. The DRM driver has no business<br>
> > controlling the EMC clock directly. This should be done through a real<br>
> > EMC driver plus some kind of bus QoS, where DC is just one client.<br>
><br>
> I thought about it but didn't see another consumer in upstream<br>
> kernels. Who are the other consumers of EMC?<br>
<br>
</div>There are no other EMC consumers upstream at the moment. Some recent<br>
discussions also indicate that it's unlikely that EMC scaling will be<br>
implemented using shared clocks upstream.<br>
<br>
See here for the full description:<br>
<br>
<a href="https://lkml.org/lkml/2014/5/13/469" target="_blank">https://lkml.org/lkml/2014/5/13/469</a></blockquote><div><br></div><div>So if keeping the EMC clock private is a no-go, and shared clocks are also a no-go, should I just make a separate one-off driver just for EMC and call into that?<br>
</div><div><br></div><div>Stéphane</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
<br>
Also adding linux-tegra to Cc. I like to keep that list in the loop for<br>
patches that touch the Tegra DRM driver. That's especially useful if<br>
other APIs are involved (such as clocks here).<br>
<br>
Thierry<br>
<br>
><br>
> Stéphane<br>
><br>
><br>
> Regards,<br>
> Lucas<br>
><br>
> > Signed-off-by: Stéphane Marchesin <<a href="mailto:marcheu@chromium.org">marcheu@chromium.org</a><mailto:<a href="mailto:marcheu@chromium.org">marcheu@chromium.org</a>>><br>
<div><div class="h5">> > ---<br>
> > drivers/gpu/drm/tegra/dc.c | 61 ++++++++++++++++++++++++++++++++++++++++++++-<br>
> > drivers/gpu/drm/tegra/drm.h | 1 +<br>
> > 2 files changed, 61 insertions(+), 1 deletion(-)<br>
> ><br>
> > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c<br>
> > index edb871d..f398dfb 100644<br>
> > --- a/drivers/gpu/drm/tegra/dc.c<br>
> > +++ b/drivers/gpu/drm/tegra/dc.c<br>
> > @@ -325,6 +325,9 @@ static void tegra_crtc_disable(struct drm_crtc *crtc)<br>
> > }<br>
> ><br>
> > drm_vblank_off(drm, dc->pipe);<br>
> > +<br>
> > + if (dc->emc_clk)<br>
> > + clk_set_rate(dc->emc_clk, 0);<br>
> > }<br>
> ><br>
> > static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,<br>
> > @@ -640,6 +643,50 @@ unsigned int tegra_dc_format(uint32_t format)<br>
> > return WIN_COLOR_DEPTH_B8G8R8A8;<br>
> > }<br>
> ><br>
> > +static unsigned long tegra_emc_bw_to_freq_req(unsigned long bw)<br>
> > +{<br>
> > + int bytes_per_emc_clock;<br>
> > +<br>
> > + if (of_machine_is_compatible("nvidia,tegra124"))<br>
> > + bytes_per_emc_clock = 16;<br>
> > + else<br>
> > + bytes_per_emc_clock = 8;<br>
> > +<br>
> > + return (bw + bytes_per_emc_clock - 1) / bytes_per_emc_clock;<br>
> > +}<br>
> > +<br>
> > +#define EMC_FREQ_CUTOFF_USE_130_PERCENT 100000000UL<br>
> > +#define EMC_FREQ_CUTOFF_USE_140_PERCENT 50000000UL<br>
> > +<br>
> > +static int tegra_dc_program_bandwidth(struct tegra_dc *dc,<br>
> > + struct drm_display_mode *mode,<br>
> > + struct tegra_dc_window *window)<br>
> > +{<br>
> > + unsigned long bandwidth = mode->clock * window->bits_per_pixel / 8;<br>
> > + unsigned long freq;<br>
> > + struct clk *emc_master;<br>
> > +<br>
> > + if (!dc->emc_clk)<br>
> > + return 0;<br>
> > +<br>
> > + emc_master = clk_get_parent(dc->emc_clk);<br>
> > + freq = tegra_emc_bw_to_freq_req(bandwidth) * 1000;<br>
> > + freq = clk_round_rate(emc_master, freq);<br>
> > +<br>
> > + /* XXX: Add safety margins for DVFS */<br>
> > +<br>
> > + if (freq < EMC_FREQ_CUTOFF_USE_140_PERCENT)<br>
> > + bandwidth += 4 * bandwidth / 10;<br>
> > + else if (freq < EMC_FREQ_CUTOFF_USE_130_PERCENT)<br>
> > + bandwidth += 3 * bandwidth / 10;<br>
> > + else<br>
> > + bandwidth += bandwidth / 10;<br>
> > +<br>
> > + freq = tegra_emc_bw_to_freq_req(bandwidth) * 1000;<br>
> > +<br>
> > + return clk_set_rate(dc->emc_clk, freq);<br>
> > +}<br>
> > +<br>
> > static int tegra_crtc_mode_set(struct drm_crtc *crtc,<br>
> > struct drm_display_mode *mode,<br>
> > struct drm_display_mode *adjusted,<br>
> > @@ -691,7 +738,11 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc,<br>
> > if (err < 0)<br>
> > dev_err(dc->dev, "failed to enable root plane\n");<br>
> ><br>
> > - return 0;<br>
> > + err = tegra_dc_program_bandwidth(dc, mode, &window);<br>
> > + if (err)<br>
> > + dev_err(dc->dev, "failed to program the EMC clock\n");<br>
> > +<br>
> > + return err;<br>
> > }<br>
> ><br>
> > static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,<br>
> > @@ -1260,6 +1311,12 @@ static int tegra_dc_probe(struct platform_device *pdev)<br>
> > if (err < 0)<br>
> > return err;<br>
> ><br>
> > + dc->emc_clk = devm_clk_get(&pdev->dev, "emc");<br>
> > + if (IS_ERR(dc->emc_clk))<br>
> > + dc->emc_clk = NULL;<br>
> > + else<br>
> > + clk_prepare_enable(dc->emc_clk);<br>
> > +<br>
> > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);<br>
> > dc->regs = devm_ioremap_resource(&pdev->dev, regs);<br>
> > if (IS_ERR(dc->regs))<br>
> > @@ -1312,6 +1369,8 @@ static int tegra_dc_remove(struct platform_device *pdev)<br>
> > }<br>
> ><br>
> > clk_disable_unprepare(dc->clk);<br>
> > + if (dc->emc_clk)<br>
> > + clk_disable_unprepare(dc->emc_clk);<br>
> ><br>
> > return 0;<br>
> > }<br>
> > diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h<br>
> > index 6753598..30d91c0 100644<br>
> > --- a/drivers/gpu/drm/tegra/drm.h<br>
> > +++ b/drivers/gpu/drm/tegra/drm.h<br>
> > @@ -101,6 +101,7 @@ struct tegra_dc {<br>
> ><br>
> > struct clk *clk;<br>
> > struct reset_control *rst;<br>
> > + struct clk *emc_clk;<br>
> > void __iomem *regs;<br>
> > int irq;<br>
> ><br>
><br>
> --<br>
> Pengutronix e.K. | Lucas Stach |<br>
> Industrial Linux Solutions | <a href="http://www.pengutronix.de/" target="_blank">http://www.pengutronix.de/</a> |<br>
><br>
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</blockquote></div><br></div></div>