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<base href="https://bugs.freedesktop.org/" />
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<th>Priority</th>
<td>medium
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [r600g, bisected] multiple ubo piglit regressions"
href="https://bugs.freedesktop.org/show_bug.cgi?id=82139">82139</a>
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<th>Assignee</th>
<td>dri-devel@lists.freedesktop.org
</td>
</tr>
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<th>Summary</th>
<td>[r600g, bisected] multiple ubo piglit regressions
</td>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Classification</th>
<td>Unclassified
</td>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Reporter</th>
<td>andreas.boll.dev@gmail.com
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<th>Hardware</th>
<td>Other
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Version</th>
<td>git
</td>
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<th>Component</th>
<td>Drivers/Gallium/r600
</td>
</tr>
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<th>Product</th>
<td>Mesa
</td>
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<pre>I noticed multiple ubo piglit regressions on 10.3-devel / r600g / BARTS
since this commit:
commit 01bf8bb87565ed3677e43c6b6deeb90378d88647
Author: Brian Paul <<a href="mailto:brianp@vmware.com">brianp@vmware.com</a>>
Date: Tue Jul 1 07:57:43 2014 -0600
st/mesa: don't use address register for constant-indexed ir_binop_ubo_load
Before, we were always using the address register and indirect addressing
to index into a UBO constant buffer. With this change we only do that
when necessary.
Using the piglit bin/arb_uniform_buffer_object-rendering test as an
example:
Shader code:
uniform ub_rot {float rotation; };
...
m[1][1] = cos(rotation);
Before:
IMM[1] INT32 {0, 1, 0, 0}
1: UARL ADDR[0].x, IMM[1].xxxx
2: MOV TEMP[0].x, CONST[3][ADDR[0].x].xxxx
3: COS TEMP[1].x, TEMP[0].xxxx
After:
0: COS TEMP[0].x, CONST[3][0].xxxx
Reviewed-by: Roland Scheidegger <<a href="mailto:sroland@vmware.com">sroland@vmware.com</a>>
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index d660a6b..69d67e1 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -1971,9 +1971,17 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
assert(ir->type->is_vector() || ir->type->is_scalar());
if (const_offset_ir) {
- index_reg = st_src_reg_for_int(const_offset / 16);
- } else {
- emit(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), op[1],
st_src_reg_for_int(4));
+ /* Constant index into constant buffer */
+ cbuf.reladdr = NULL;
+ cbuf.index = const_offset / 16;
+ cbuf.has_index2 = true;
+ }
+ else {
+ /* Relative/variable index into constant buffer */
+ emit(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), op[1],
+ st_src_reg_for_int(4));
+ cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
+ memcpy(cbuf.reladdr, &index_reg, sizeof(index_reg));
}
cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
@@ -1982,9 +1990,6 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
const_offset % 16 / 4,
const_offset % 16 / 4);
- cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
- memcpy(cbuf.reladdr, &index_reg, sizeof(index_reg));
-
if (ir->type->base_type == GLSL_TYPE_BOOL) {
emit(ir, TGSI_OPCODE_USNE, result_dst, cbuf, st_src_reg_for_int(0));
} else {
I guess it unhides a driver bug, since softpipe and llvmpipe are not affected.
Regressed tests:
spec/ARB_uniform_buffer_object/bufferstorage
spec/ARB_uniform_buffer_object/maxblocks
spec/ARB_uniform_buffer_object/rendering
spec/glsl-1.40/uniform_buffer/fs-mat4
spec/glsl-1.40/uniform_buffer/fs-two-members
spec/glsl-1.40/uniform_buffer/vs-mat4
spec/glsl-1.40/uniform_buffer/vs-two-members
spec/glsl-1.50/uniform_buffer/gs-mat4
spec/glsl-1.50/uniform_buffer/gs-two-members
Thanks,
Andreas.</pre>
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