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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - R9270X pyrit benchmark perf regressions with latest kernel/llvm"
href="https://bugs.freedesktop.org/show_bug.cgi?id=82050#c8">Comment # 8</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - R9270X pyrit benchmark perf regressions with latest kernel/llvm"
href="https://bugs.freedesktop.org/show_bug.cgi?id=82050">bug 82050</a>
from <span class="vcard"><a class="email" href="mailto:adf.lists@gmail.com" title="Andy Furniss <adf.lists@gmail.com>"> <span class="fn">Andy Furniss</span></a>
</span></b>
<pre>kernel -
fb240a2534802a86742db51b7334138675bc435e is the first bad commit
commit fb240a2534802a86742db51b7334138675bc435e
Author: Michel Dänzer <<a href="mailto:michel.daenzer@amd.com">michel.daenzer@amd.com</a>>
Date: Thu Jul 31 18:43:49 2014 +0900
drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <<a href="mailto:michel.daenzer@amd.com">michel.daenzer@amd.com</a>>
Signed-off-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>></pre>
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