<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c16">Comment # 16</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a> from <a class="email" href="mailto:alexdeucher@gmail.com" title="Alex Deucher <alexdeucher@gmail.com>"> Alex Deucher</a> <pre>(In reply to Christian König from <a href="show_bug.cgi?id=73378#c14">comment #14</a>) > (In reply to Öyvind Saether from <a href="show_bug.cgi?id=73378#c13">comment #13</a>) > > on 3.18.1, could this be because the card is factory overclocked? > > Yes, that's possible. If you activate UVD you must downclock the system > clock for it to work reliable. Not sure if we have implemented that > correctly for SI. We already handle it. SI has UVD power states which also include validated sclk and mclk levels that are often different than the performance state. The driver switches to those states when UVD is used. At driver load time (when the ring and IB tests are done), the hw is still in the boot state (which has really low clocks) anyway.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>