<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c17">Comment # 17</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a> from <a class="email" href="mailto:alexdeucher@gmail.com" title="Alex Deucher <alexdeucher@gmail.com>"> Alex Deucher</a> <pre>On older versions of the driver we init dpm after everything else, so the ring and ib tests happen before we even touch the dpm hw so clocks are at their low boot up levels. On newer versions of the driver we init dpm early, but we don't enable the non boot states until the end of the init sequence after the ring and ib tests. >From the log: [ 5.237881] == power state 0 == [ 5.237882] ui class: none [ 5.237883] internal class: boot [ 5.237884] caps: [ 5.237885] uvd vclk: 0 dclk: 0 [ 5.237887] power level 0 sclk: 15000 mclk: 15000 vddc: 900 vddci: 950 pcie gen: 2 [ 5.237887] status: c r b This is the boot state. The clocks are fixed at 150Mhz for both sclk and mclk. [ 5.237889] == power state 1 == [ 5.237890] ui class: performance [ 5.237890] internal class: none [ 5.237891] caps: [ 5.237892] uvd vclk: 0 dclk: 0 [ 5.237893] power level 0 sclk: 30000 mclk: 15000 vddc: 825 vddci: 850 pcie gen: 2 [ 5.237895] power level 1 sclk: 45000 mclk: 120000 vddc: 900 vddci: 975 pcie gen: 2 [ 5.237896] power level 2 sclk: 100000 mclk: 120000 vddc: 1219 vddci: 975 pcie gen: 2 [ 5.237896] status: This is the performance state. The sclk can range from 300 Mhz to 1Ghz and the mclk can range from 150Mhz to 1.2Ghz based on GPU demand. [ 5.237897] == power state 2 == [ 5.237898] ui class: none [ 5.237898] internal class: uvd [ 5.237899] caps: video [ 5.237901] uvd vclk: 72000 dclk: 56000 [ 5.237902] power level 0 sclk: 45000 mclk: 120000 vddc: 900 vddci: 975 pcie gen: 2 [ 5.237903] power level 1 sclk: 45000 mclk: 120000 vddc: 900 vddci: 975 pcie gen: 2 [ 5.237904] power level 2 sclk: 100000 mclk: 120000 vddc: 1219 vddci: 975 pcie gen: 2 [ 5.237905] status: This is the UVD state. As you can see there is a floor of 450Mhz on the sclk to maintain the necessary performance level for post processing and presentation. [ 5.237905] == power state 3 == [ 5.237906] ui class: none [ 5.237907] internal class: ulv [ 5.237908] caps: [ 5.237909] uvd vclk: 0 dclk: 0 [ 5.237910] power level 0 sclk: 30000 mclk: 15000 vddc: 825 vddci: 850 pcie gen: 2 [ 5.237911] power level 1 sclk: 30000 mclk: 15000 vddc: 825 vddci: 850 pcie gen: 2 [ 5.237912] power level 2 sclk: 30000 mclk: 15000 vddc: 825 vddci: 850 pcie gen: 2 This is the ulv state which is only active when the board is completely idle.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>