<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c19">Comment # 19</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a> from <a class="email" href="mailto:alexdeucher@gmail.com" title="Alex Deucher <alexdeucher@gmail.com>"> Alex Deucher</a> <pre>(In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c18">comment #18</a>) > Hm-m, just tried drm-next-3.20 branch and: > > [ 365.200918] [drm:radeon_uvd_send_upll_ctlreq [radeon]] *ERROR* Timeout > setting UVD clocks! > [ 365.200922] [drm:uvd_v1_0_ib_test [radeon]] *ERROR* radeon: failed to > raise UVD clocks (-110). > [ 365.200928] [drm:radeon_ib_ring_tests [radeon]] *ERROR* radeon: failed > testing IB on ring 5 (-110). > > > Both on cold start and resume from suspend, Pitcairn, Mesa 10.4.3 > Ah yes, the card is factory overclocked (at least box states so) > > It's not very painful for me but if I can help somehow, I'm in I don't think it will make a difference, but you can try limiting the clocks in si_apply_state_adjust_rules(). Take a look at the quirk handling code for how to limit the sclk and mclk.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>