<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c20">Comment # 20</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a> from <a class="email" href="mailto:deathsimple@vodafone.de" title="Christian König <deathsimple@vodafone.de>"> Christian König</a> <pre>(In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c15">comment #15</a>) > I can help with code here. > > What should be implemented, roughly? Sounds good. I assume you got a card with that problem. First of all try if UVD works otherwise. E.g. we raise the clocks for the boot up test (and lower them again after that), but that's actually not necessary most of the time. So get into radeon_uvd_send_upll_ctlreq, just comment out the error return value and pretend everything worked fine. Then check if the following IB test works or not. If that doesn't work the input clocks to the PLL doesn't seem to work and we have a clock routing problem or something like that. If that works the PLL just doesn't likes our parameters and we need to figure out why. Feel free to contact me by mail if you have more questions. Thanks, Christian.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>