<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c24">Comment # 24</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a> from <a class="email" href="mailto:deathsimple@vodafone.de" title="Christian König <deathsimple@vodafone.de>"> Christian König</a> <pre>(In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c23">comment #23</a>) > Wow! Pls forget my last comment completely. > > Just tried to watch H264 video and it was slow as hell :( Which is the espected result if you don't setup the clocks :) In this case the UVD block runs with the default 100Mhz instead of the desired 400,500,900 or whatever the power tables say we should programm it to. At least we now knew that the input frequency works well. Now take a look at si_set_uvd_clocks in si.c. Especially try to figure out if the first or the second call to radeon_uvd_send_upll_ctlreq fails. Additional to that please install radeontool and get me the content of the CG_UPLL_* registers. E.g. I need the output of: radeontool regmatch 0x634 radeontool regmatch 0x638 radeontool regmatch 0x63c radeontool regmatch 0x644 radeontool regmatch 0x648 radeontool regmatch 0x650 Thanks, Christian.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>