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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c25">Comment # 25</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a>
from <span class="vcard"><a class="email" href="mailto:adonai@xaker.ru" title="Chernovsky Oleg <adonai@xaker.ru>"> <span class="fn">Chernovsky Oleg</span></a>
</span></b>
<pre>(In reply to Christian König from <a href="show_bug.cgi?id=73378#c24">comment #24</a>)
<span class="quote">> Now take a look at si_set_uvd_clocks in si.c. Especially try to figure out
> if the first or the second call to radeon_uvd_send_upll_ctlreq fails.
>
> Additional to that please install radeontool and get me the content of the
> CG_UPLL_* registers. E.g. I need the output of:
>
> radeontool regmatch 0x634
> radeontool regmatch 0x638
> radeontool regmatch 0x63c
> radeontool regmatch 0x644
> radeontool regmatch 0x648
> radeontool regmatch 0x650
>
> Thanks,
> Christian.</span >
It's the first call to this function in si_set_uvd_clocks that's failing.
Doesn't work in bypass mode? Or maybe too low mdelay before call?
[ 2.237380] [drm] At call 1
[ 3.278457] [drm] At call 2
[ 3.288474] [drm] Passed!
Registers dump:
0x634 0x00000706 (1798)
0x638 0x021e0403 (35521539)
0x63c 0x100ece38 (269405752)
0x644 0x00820000 (8519680)
0x648 0x00000000 (0)</pre>
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