<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c27">Comment # 27</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!" href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a> from <a class="email" href="mailto:deathsimple@vodafone.de" title="Christian König <deathsimple@vodafone.de>"> Christian König</a> <pre>(In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c25">comment #25</a>) > It's the first call to this function in si_set_uvd_clocks that's failing. > Doesn't work in bypass mode? Or maybe too low mdelay before call? > > [ 2.237380] [drm] At call 1 > [ 3.278457] [drm] At call 2 > [ 3.288474] [drm] Passed! Well just that I got it right: The first call runs into an error, but after issuing the reset and reprogramming everything the second call succeeds? In this case I would just speculate that somebody (the BIOS?) programmed the PLL with such incorrect values that it locked up and need a reset to work properly again. Can you just reduce the first call to radeon_uvd_send_upll_ctlreq to a warning and continue? If the second call works we have successfully programmed the PLL and everything is fine.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>