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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c30">Comment # 30</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a>
from <span class="vcard"><a class="email" href="mailto:deathsimple@vodafone.de" title="Christian König <deathsimple@vodafone.de>"> <span class="fn">Christian König</span></a>
</span></b>
<pre>(In reply to Chernovsky Oleg from <a href="show_bug.cgi?id=73378#c29">comment #29</a>)
<span class="quote">> No luck. Tried various hacks and commenting return values.
>
> Will try mmiotracing these registers from fglrx on weekend</span >
Be careful that to write no irrational values into the PLL registers, e.g.
don't use partly radeon partly fglrx settings.
I once over clocked UVD to 4GHz instead of 400MHz by accident and the card is
still working, but at least in theory you can damage the hardware with that.</pre>
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