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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378#c33">Comment # 33</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!"
href="https://bugs.freedesktop.org/show_bug.cgi?id=73378">bug 73378</a>
from <span class="vcard"><a class="email" href="mailto:adonai@xaker.ru" title="Chernovsky Oleg <adonai@xaker.ru>"> <span class="fn">Chernovsky Oleg</span></a>
</span></b>
<pre>Yep, I rechecked it and it seems set to 1 always...
Anyway I gathered around 18 Mb of mmiotrace logs to investigate. Now digging
through divider and clock registers.
P.S. I only fear that maybe I launched mmiotrace too late, I did rmmod and then
modprobe fglrx again. Could it setup any registers at the first run? Because at
second it touched UVD only when I launched mpv.</pre>
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